base_dyn_inst.hh revision 11097
11060SN/A/* 29814Sandreas.hansson@arm.com * Copyright (c) 2011,2013 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 4910835Sandreas.hansson@arm.com#include <array> 502731Sktlim@umich.edu#include <bitset> 512292SN/A#include <list> 521464SN/A#include <string> 538733Sgeoffrey.blake@arm.com#include <queue> 541060SN/A 5510687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 567720Sgblack@eecs.umich.edu#include "arch/utility.hh" 571060SN/A#include "base/trace.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 598887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 603770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 6110319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 621464SN/A#include "cpu/exetrace.hh" 631464SN/A#include "cpu/inst_seq.hh" 642669Sktlim@umich.edu#include "cpu/op_class.hh" 651060SN/A#include "cpu/static_inst.hh" 666973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 672669Sktlim@umich.edu#include "mem/packet.hh" 687678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 692292SN/A#include "sim/system.hh" 701060SN/A 711060SN/A/** 721060SN/A * @file 731060SN/A * Defines a dynamic instruction context. 741060SN/A */ 751060SN/A 761060SN/Atemplate <class Impl> 7710319SAndreas.Sandberg@ARM.comclass BaseDynInst : public ExecContext, public RefCounted 781060SN/A{ 791060SN/A public: 801060SN/A // Typedef for the CPU. 812733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 822733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 831060SN/A 842292SN/A // Logical register index type. 852107SN/A typedef TheISA::RegIndex RegIndex; 861060SN/A 872292SN/A // The DynInstPtr type. 882292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 898486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 902292SN/A 912292SN/A // The list of instructions iterator type. 922292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 932292SN/A 941060SN/A enum { 955543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 968902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 971060SN/A }; 981060SN/A 999046SAli.Saidi@ARM.com union Result { 1009046SAli.Saidi@ARM.com uint64_t integer; 1019046SAli.Saidi@ARM.com double dbl; 1029046SAli.Saidi@ARM.com void set(uint64_t i) { integer = i; } 1039046SAli.Saidi@ARM.com void set(double d) { dbl = d; } 1049046SAli.Saidi@ARM.com void get(uint64_t& i) { i = integer; } 1059046SAli.Saidi@ARM.com void get(double& d) { d = dbl; } 1069046SAli.Saidi@ARM.com }; 1079046SAli.Saidi@ARM.com 1089046SAli.Saidi@ARM.com protected: 1099046SAli.Saidi@ARM.com enum Status { 1109046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1119046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1129046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1139046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1149046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1159046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1169046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1179046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1189046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1199046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1209046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1219046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1229046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1239046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1249046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1259046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1269046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1279046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1289046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1299046SAli.Saidi@ARM.com /// instructions ahead of it 1309046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1319046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1329046SAli.Saidi@ARM.com NumStatus 1339046SAli.Saidi@ARM.com }; 1349046SAli.Saidi@ARM.com 1359046SAli.Saidi@ARM.com enum Flags { 1369046SAli.Saidi@ARM.com TranslationStarted, 1379046SAli.Saidi@ARM.com TranslationCompleted, 1389046SAli.Saidi@ARM.com PossibleLoadViolation, 1399046SAli.Saidi@ARM.com HitExternalSnoop, 1409046SAli.Saidi@ARM.com EffAddrValid, 1419046SAli.Saidi@ARM.com RecordResult, 1429046SAli.Saidi@ARM.com Predicate, 1439046SAli.Saidi@ARM.com PredTaken, 1449046SAli.Saidi@ARM.com /** Whether or not the effective address calculation is completed. 1459046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 1469046SAli.Saidi@ARM.com */ 1479046SAli.Saidi@ARM.com EACalcDone, 14810824SAndreas.Sandberg@ARM.com IsStrictlyOrdered, 1499046SAli.Saidi@ARM.com ReqMade, 1509046SAli.Saidi@ARM.com MemOpDone, 1519046SAli.Saidi@ARM.com MaxFlags 1529046SAli.Saidi@ARM.com }; 1539046SAli.Saidi@ARM.com 1549046SAli.Saidi@ARM.com public: 1559046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1569046SAli.Saidi@ARM.com InstSeqNum seqNum; 1579046SAli.Saidi@ARM.com 1582292SN/A /** The StaticInst used by this BaseDynInst. */ 15910417Sandreas.hansson@arm.com const StaticInstPtr staticInst; 1609046SAli.Saidi@ARM.com 1619046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1629046SAli.Saidi@ARM.com ImplCPU *cpu; 1639046SAli.Saidi@ARM.com 16410030SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return cpu; } 16510030SAli.Saidi@ARM.com 1669046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1679046SAli.Saidi@ARM.com ImplState *thread; 1689046SAli.Saidi@ARM.com 1699046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1709046SAli.Saidi@ARM.com Fault fault; 1719046SAli.Saidi@ARM.com 1729046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1739046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1749046SAli.Saidi@ARM.com 1759046SAli.Saidi@ARM.com protected: 1769046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1779046SAli.Saidi@ARM.com * destination registers. 1789046SAli.Saidi@ARM.com */ 1799046SAli.Saidi@ARM.com std::queue<Result> instResult; 1809046SAli.Saidi@ARM.com 1819046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1829046SAli.Saidi@ARM.com TheISA::PCState pc; 1839046SAli.Saidi@ARM.com 1849046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1859046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1869046SAli.Saidi@ARM.com 1879046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1889046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1899046SAli.Saidi@ARM.com 1909046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1919046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1929046SAli.Saidi@ARM.com */ 1939046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1949046SAli.Saidi@ARM.com 1959046SAli.Saidi@ARM.com public: 1969046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 1979046SAli.Saidi@ARM.com ThreadID threadNumber; 1989046SAli.Saidi@ARM.com 1999046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 2009046SAli.Saidi@ARM.com ListIt instListIt; 2019046SAli.Saidi@ARM.com 2029046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 2039046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 2049046SAli.Saidi@ARM.com TheISA::PCState predPC; 2059046SAli.Saidi@ARM.com 2069046SAli.Saidi@ARM.com /** The Macroop if one exists */ 20710417Sandreas.hansson@arm.com const StaticInstPtr macroop; 2081060SN/A 2099046SAli.Saidi@ARM.com /** How many source registers are ready. */ 2109046SAli.Saidi@ARM.com uint8_t readyRegs; 2119046SAli.Saidi@ARM.com 2129046SAli.Saidi@ARM.com public: 2139046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2149046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2159046SAli.Saidi@ARM.com Addr effAddr; 2169046SAli.Saidi@ARM.com 2179046SAli.Saidi@ARM.com /** The effective physical address. */ 21811097Songal@cs.wisc.edu Addr physEffAddrLow; 21911097Songal@cs.wisc.edu 22011097Songal@cs.wisc.edu /** The effective physical address 22111097Songal@cs.wisc.edu * of the second request for a split request 22211097Songal@cs.wisc.edu */ 22311097Songal@cs.wisc.edu Addr physEffAddrHigh; 2249046SAli.Saidi@ARM.com 2259046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2269046SAli.Saidi@ARM.com unsigned memReqFlags; 2279046SAli.Saidi@ARM.com 2289046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2299046SAli.Saidi@ARM.com short asid; 2309046SAli.Saidi@ARM.com 2319046SAli.Saidi@ARM.com /** The size of the request */ 2329046SAli.Saidi@ARM.com uint8_t effSize; 2339046SAli.Saidi@ARM.com 2349046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2359046SAli.Saidi@ARM.com uint8_t *memData; 2369046SAli.Saidi@ARM.com 2379046SAli.Saidi@ARM.com /** Load queue index. */ 2389046SAli.Saidi@ARM.com int16_t lqIdx; 2399046SAli.Saidi@ARM.com 2409046SAli.Saidi@ARM.com /** Store queue index. */ 2419046SAli.Saidi@ARM.com int16_t sqIdx; 2429046SAli.Saidi@ARM.com 2439046SAli.Saidi@ARM.com 2449046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2459046SAli.Saidi@ARM.com /** 2469046SAli.Saidi@ARM.com * Saved memory requests (needed when the DTB address translation is 2479046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2489046SAli.Saidi@ARM.com */ 2499046SAli.Saidi@ARM.com RequestPtr savedReq; 2509046SAli.Saidi@ARM.com RequestPtr savedSreqLow; 2519046SAli.Saidi@ARM.com RequestPtr savedSreqHigh; 2529046SAli.Saidi@ARM.com 2539046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2549046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2559046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2569046SAli.Saidi@ARM.com 2579046SAli.Saidi@ARM.com private: 2589046SAli.Saidi@ARM.com /** Instruction effective address. 2599046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 2609046SAli.Saidi@ARM.com */ 2619046SAli.Saidi@ARM.com Addr instEffAddr; 2629046SAli.Saidi@ARM.com 2639046SAli.Saidi@ARM.com protected: 2649046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2659046SAli.Saidi@ARM.com * instruction. 2669046SAli.Saidi@ARM.com */ 26710835Sandreas.hansson@arm.com std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2689046SAli.Saidi@ARM.com 2699046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2709046SAli.Saidi@ARM.com * instruction. 2719046SAli.Saidi@ARM.com */ 27210835Sandreas.hansson@arm.com std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx; 2739046SAli.Saidi@ARM.com 2749046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2759046SAli.Saidi@ARM.com * instruction. 2769046SAli.Saidi@ARM.com */ 27710835Sandreas.hansson@arm.com std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx; 2789046SAli.Saidi@ARM.com 2799046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2809046SAli.Saidi@ARM.com * architected destinations. 2819046SAli.Saidi@ARM.com */ 28210835Sandreas.hansson@arm.com std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2839046SAli.Saidi@ARM.com 2849046SAli.Saidi@ARM.com 2859046SAli.Saidi@ARM.com public: 2869046SAli.Saidi@ARM.com /** Records changes to result? */ 2879046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2889046SAli.Saidi@ARM.com 2899046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2909046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 2919046SAli.Saidi@ARM.com 2929046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2939046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2949046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2959046SAli.Saidi@ARM.com 2969046SAli.Saidi@ARM.com 2971060SN/A //////////////////////////////////////////// 2981060SN/A // 2991060SN/A // INSTRUCTION EXECUTION 3001060SN/A // 3011060SN/A //////////////////////////////////////////// 3021060SN/A 3035358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3045358Sgblack@eecs.umich.edu { 3055358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3065358Sgblack@eecs.umich.edu } 3075358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3085358Sgblack@eecs.umich.edu { 3095358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3105358Sgblack@eecs.umich.edu } 3115358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3125358Sgblack@eecs.umich.edu { 3135358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3145358Sgblack@eecs.umich.edu } 3155358Sgblack@eecs.umich.edu 3168444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3177520Sgblack@eecs.umich.edu 3188444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 3198444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 3207520Sgblack@eecs.umich.edu 3216974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 3226974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3236974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 3246974Stjones1@inf.ed.ac.uk 3256973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 3266974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3276974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 3286973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 3296973Stjones1@inf.ed.ac.uk 3306973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 3316973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3321060SN/A 3337944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3349046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3359046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3367944SGiacomo.Gabrielli@arm.com 3377944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3389046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3399046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3407944SGiacomo.Gabrielli@arm.com 3418545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3428545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3438545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3448545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3458545Ssaidi@eecs.umich.edu */ 3469046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3479046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3488545Ssaidi@eecs.umich.edu 3498545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3508545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3518545Ssaidi@eecs.umich.edu * reexecute 3528545Ssaidi@eecs.umich.edu */ 3539046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3549046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3558545Ssaidi@eecs.umich.edu 3567944SGiacomo.Gabrielli@arm.com /** 3577944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3587944SGiacomo.Gabrielli@arm.com * page table walk. 3597944SGiacomo.Gabrielli@arm.com */ 3607944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3617944SGiacomo.Gabrielli@arm.com { 3629046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3637944SGiacomo.Gabrielli@arm.com } 3647944SGiacomo.Gabrielli@arm.com 3651060SN/A public: 3662292SN/A#ifdef DEBUG 3672292SN/A void dumpSNList(); 3682292SN/A#endif 3692292SN/A 3703770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3713770Sgblack@eecs.umich.edu * register. 3723770Sgblack@eecs.umich.edu */ 3733770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3743770Sgblack@eecs.umich.edu { 3753770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3763770Sgblack@eecs.umich.edu } 3773770Sgblack@eecs.umich.edu 3783770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3793770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3803770Sgblack@eecs.umich.edu { 3819046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3823770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3833770Sgblack@eecs.umich.edu } 3843770Sgblack@eecs.umich.edu 3853770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3863770Sgblack@eecs.umich.edu * register. 3873770Sgblack@eecs.umich.edu */ 3883770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3893770Sgblack@eecs.umich.edu { 3903770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3913770Sgblack@eecs.umich.edu } 3923770Sgblack@eecs.umich.edu 3933770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3943770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3953770Sgblack@eecs.umich.edu */ 3963770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3973770Sgblack@eecs.umich.edu { 3983770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3993770Sgblack@eecs.umich.edu } 4003770Sgblack@eecs.umich.edu 4013770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 4023770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 4033770Sgblack@eecs.umich.edu */ 4043770Sgblack@eecs.umich.edu void renameDestReg(int idx, 4053770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 4063770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 4073770Sgblack@eecs.umich.edu { 4083770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 4093770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 4103770Sgblack@eecs.umich.edu } 4113770Sgblack@eecs.umich.edu 4123770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 4133770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 4143770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 4153770Sgblack@eecs.umich.edu */ 4163770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 4173770Sgblack@eecs.umich.edu { 4183770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 4193770Sgblack@eecs.umich.edu } 4203770Sgblack@eecs.umich.edu 4213770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 4223770Sgblack@eecs.umich.edu * index. 4233770Sgblack@eecs.umich.edu */ 4243770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 4253770Sgblack@eecs.umich.edu { 4263770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4273770Sgblack@eecs.umich.edu } 4284636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4294636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4307720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4317720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4324636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4334636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4344636Sgblack@eecs.umich.edu */ 43510417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4368502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4378502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4383770Sgblack@eecs.umich.edu 4392292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4402292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4412292SN/A */ 44210417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4431060SN/A 4441060SN/A /** BaseDynInst destructor. */ 4451060SN/A ~BaseDynInst(); 4461060SN/A 4471464SN/A private: 4481684SN/A /** Function to initialize variables in the constructors. */ 4491464SN/A void initVars(); 4501060SN/A 4511464SN/A public: 4521060SN/A /** Dumps out contents of this BaseDynInst. */ 4531060SN/A void dump(); 4541060SN/A 4551060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4561060SN/A void dump(std::string &outstring); 4571060SN/A 4583326Sktlim@umich.edu /** Read this CPU's ID. */ 45910110Sandreas.hansson@arm.com int cpuId() const { return cpu->cpuId(); } 4603326Sktlim@umich.edu 46110190Sakash.bagdia@arm.com /** Read this CPU's Socket ID. */ 46210190Sakash.bagdia@arm.com uint32_t socketId() const { return cpu->socketId(); } 46310190Sakash.bagdia@arm.com 4648832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 46510110Sandreas.hansson@arm.com MasterID masterId() const { return cpu->dataMasterId(); } 4668832SAli.Saidi@ARM.com 4675714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 46811005Sandreas.sandberg@arm.com ContextID contextId() const { return thread->contextId(); } 4695714Shsul@eecs.umich.edu 4701060SN/A /** Returns the fault type. */ 47110110Sandreas.hansson@arm.com Fault getFault() const { return fault; } 4721060SN/A 4731060SN/A /** Checks whether or not this instruction has had its branch target 4741060SN/A * calculated yet. For now it is not utilized and is hacked to be 4751060SN/A * always false. 4762292SN/A * @todo: Actually use this instruction. 4771060SN/A */ 4781060SN/A bool doneTargCalc() { return false; } 4791060SN/A 4807720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4817720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4823965Sgblack@eecs.umich.edu { 4837720Sgblack@eecs.umich.edu predPC = _predPC; 4843965Sgblack@eecs.umich.edu } 4852935Sksewell@umich.edu 4867720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4871060SN/A 4883794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4897720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4903794Sgblack@eecs.umich.edu 4913794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4927720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4931060SN/A 4944636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4957720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4964636Sgblack@eecs.umich.edu 4971060SN/A /** Returns whether the instruction was predicted taken or not. */ 4983794Sgblack@eecs.umich.edu bool readPredTaken() 4993794Sgblack@eecs.umich.edu { 5009046SAli.Saidi@ARM.com return instFlags[PredTaken]; 5013794Sgblack@eecs.umich.edu } 5023794Sgblack@eecs.umich.edu 5033794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 5043794Sgblack@eecs.umich.edu { 5059046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 5063794Sgblack@eecs.umich.edu } 5071060SN/A 5081060SN/A /** Returns whether the instruction mispredicted. */ 5092935Sksewell@umich.edu bool mispredicted() 5103794Sgblack@eecs.umich.edu { 5117720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 5127720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 5137720Sgblack@eecs.umich.edu return !(tempPC == predPC); 5143794Sgblack@eecs.umich.edu } 5153794Sgblack@eecs.umich.edu 5161060SN/A // 5171060SN/A // Instruction types. Forward checks to StaticInst object. 5181060SN/A // 5195543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5205543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5215543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5225543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5232336SN/A bool isStoreConditional() const 5242336SN/A { return staticInst->isStoreConditional(); } 5251060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5261060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5275543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5285543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5295543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5305543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5315543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5325543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5331060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5345543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5355543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5362935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5371060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5381060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5392292SN/A bool isSerializeBefore() const 5402731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5412292SN/A bool isSerializeAfter() const 5422731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5437784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5441060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5451060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5461060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5472292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5482336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5492308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5504828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5514654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5524654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5534636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5544654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5554654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5564636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5572292SN/A 5582292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5592731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5602292SN/A 5612292SN/A /** Clears the serializeBefore part of this instruction. */ 5622731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5632292SN/A 5642292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5652731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5662292SN/A 5672292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5682731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5692292SN/A 5702292SN/A /** Clears the serializeAfter part of this instruction.*/ 5712731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5722292SN/A 5732292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5742731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5752292SN/A 5762731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5772731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5782292SN/A 5792292SN/A /** Checks if the serialization part of this instruction has been 5802292SN/A * handled. This does not apply to the temporary serializing 5812292SN/A * state; it only applies to this instruction's own permanent 5822292SN/A * serializing state. 5832292SN/A */ 5842731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5851060SN/A 5861464SN/A /** Returns the opclass of this instruction. */ 5871464SN/A OpClass opClass() const { return staticInst->opClass(); } 5881464SN/A 5891464SN/A /** Returns the branch target address. */ 5907720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5917720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5921464SN/A 5932292SN/A /** Returns the number of source registers. */ 5945543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5951684SN/A 5962292SN/A /** Returns the number of destination registers. */ 5971060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5981060SN/A 5991060SN/A // the following are used to track physical register usage 6001060SN/A // for machines with separate int & FP reg files 6011060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 6021060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 60310715SRekai.GonzalezAlberquilla@arm.com int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 6041060SN/A 6051060SN/A /** Returns the logical register index of the i'th destination register. */ 6062292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 6071060SN/A 6081060SN/A /** Returns the logical register index of the i'th source register. */ 6092292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6101060SN/A 6118733Sgeoffrey.blake@arm.com /** Pops a result off the instResult queue */ 6128733Sgeoffrey.blake@arm.com template <class T> 6138733Sgeoffrey.blake@arm.com void popResult(T& t) 6148733Sgeoffrey.blake@arm.com { 6158733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 6168733Sgeoffrey.blake@arm.com instResult.front().get(t); 6178733Sgeoffrey.blake@arm.com instResult.pop(); 6188733Sgeoffrey.blake@arm.com } 6198733Sgeoffrey.blake@arm.com } 6201684SN/A 6218733Sgeoffrey.blake@arm.com /** Read the most recent result stored by this instruction */ 6228733Sgeoffrey.blake@arm.com template <class T> 6238733Sgeoffrey.blake@arm.com void readResult(T& t) 6248733Sgeoffrey.blake@arm.com { 6258733Sgeoffrey.blake@arm.com instResult.back().get(t); 6268733Sgeoffrey.blake@arm.com } 6271684SN/A 6288733Sgeoffrey.blake@arm.com /** Pushes a result onto the instResult queue */ 6298733Sgeoffrey.blake@arm.com template <class T> 6308733Sgeoffrey.blake@arm.com void setResult(T t) 6318733Sgeoffrey.blake@arm.com { 6329046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 6338733Sgeoffrey.blake@arm.com Result instRes; 6348733Sgeoffrey.blake@arm.com instRes.set(t); 6358733Sgeoffrey.blake@arm.com instResult.push(instRes); 6368733Sgeoffrey.blake@arm.com } 6378733Sgeoffrey.blake@arm.com } 6381060SN/A 6392702Sktlim@umich.edu /** Records an integer register being set to a value. */ 64010319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 6411060SN/A { 6428733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6431060SN/A } 6441060SN/A 6459920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 64610319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6479920Syasuko.eckert@amd.com { 6489920Syasuko.eckert@amd.com setResult<uint64_t>(val); 6499920Syasuko.eckert@amd.com } 6509920Syasuko.eckert@amd.com 6512702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6523735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6531060SN/A { 6548733Sgeoffrey.blake@arm.com setResult<double>(val); 6552308SN/A } 6561060SN/A 6572702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 65810319SAndreas.Sandberg@ARM.com void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 6592308SN/A { 6608733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6611060SN/A } 6621060SN/A 6632190SN/A /** Records that one of the source registers is ready. */ 6642292SN/A void markSrcRegReady(); 6652190SN/A 6662331SN/A /** Marks a specific register as ready. */ 6672292SN/A void markSrcRegReady(RegIndex src_idx); 6682190SN/A 6691684SN/A /** Returns if a source register is ready. */ 6701464SN/A bool isReadySrcRegIdx(int idx) const 6711464SN/A { 6721464SN/A return this->_readySrcRegIdx[idx]; 6731464SN/A } 6741464SN/A 6751684SN/A /** Sets this instruction as completed. */ 6762731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6771464SN/A 6782292SN/A /** Returns whether or not this instruction is completed. */ 6792731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6801464SN/A 6812731Sktlim@umich.edu /** Marks the result as ready. */ 6822731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6832308SN/A 6842731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6852731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6862308SN/A 6871060SN/A /** Sets this instruction as ready to issue. */ 6882731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6891060SN/A 6901060SN/A /** Returns whether or not this instruction is ready to issue. */ 6912731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6921060SN/A 6934032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6944032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6954032Sktlim@umich.edu 6961060SN/A /** Sets this instruction as issued from the IQ. */ 6972731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6981060SN/A 6991060SN/A /** Returns whether or not this instruction has issued. */ 7002731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7011060SN/A 7024032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7034032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7044032Sktlim@umich.edu 7051060SN/A /** Sets this instruction as executed. */ 7062731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7071060SN/A 7081060SN/A /** Returns whether or not this instruction has executed. */ 7092731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7101060SN/A 7111060SN/A /** Sets this instruction as ready to commit. */ 7122731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7131060SN/A 7141061SN/A /** Clears this instruction as being ready to commit. */ 7152731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7161061SN/A 7171060SN/A /** Returns whether or not this instruction is ready to commit. */ 7182731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7192731Sktlim@umich.edu 7202731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7212731Sktlim@umich.edu 7222731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7231060SN/A 7242292SN/A /** Sets this instruction as committed. */ 7252731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7262292SN/A 7272292SN/A /** Returns whether or not this instruction is committed. */ 7282731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7292292SN/A 7301060SN/A /** Sets this instruction as squashed. */ 7312731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7321060SN/A 7331060SN/A /** Returns whether or not this instruction is squashed. */ 7342731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7351060SN/A 7362292SN/A //Instruction Queue Entry 7372292SN/A //----------------------- 7382292SN/A /** Sets this instruction as a entry the IQ. */ 7392731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7402292SN/A 7412292SN/A /** Sets this instruction as a entry the IQ. */ 7422731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7432731Sktlim@umich.edu 7442731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7452731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7462292SN/A 7471060SN/A /** Sets this instruction as squashed in the IQ. */ 7482731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7491060SN/A 7501060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7512731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7522292SN/A 7532292SN/A 7542292SN/A //Load / Store Queue Functions 7552292SN/A //----------------------- 7562292SN/A /** Sets this instruction as a entry the LSQ. */ 7572731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7582292SN/A 7592292SN/A /** Sets this instruction as a entry the LSQ. */ 7602731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7612731Sktlim@umich.edu 7622731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7632731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7642292SN/A 7652292SN/A /** Sets this instruction as squashed in the LSQ. */ 7662731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7672292SN/A 7682292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7692731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7702292SN/A 7712292SN/A 7722292SN/A //Reorder Buffer Functions 7732292SN/A //----------------------- 7742292SN/A /** Sets this instruction as a entry the ROB. */ 7752731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7762292SN/A 7772292SN/A /** Sets this instruction as a entry the ROB. */ 7782731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7792731Sktlim@umich.edu 7802731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7812731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7822292SN/A 7832292SN/A /** Sets this instruction as squashed in the ROB. */ 7842731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7852292SN/A 7862292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7872731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7882292SN/A 7897720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 79010319SAndreas.Sandberg@ARM.com TheISA::PCState pcState() const { return pc; } 7917720Sgblack@eecs.umich.edu 7927720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 79310319SAndreas.Sandberg@ARM.com void pcState(const TheISA::PCState &val) { pc = val; } 7947720Sgblack@eecs.umich.edu 7951060SN/A /** Read the PC of this instruction. */ 7967720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7977720Sgblack@eecs.umich.edu 7987720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7997720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 8001060SN/A 8014636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 8027720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 8034636Sgblack@eecs.umich.edu 8047597Sminkyu.jeong@arm.com bool readPredicate() 8057597Sminkyu.jeong@arm.com { 8069046SAli.Saidi@ARM.com return instFlags[Predicate]; 8077597Sminkyu.jeong@arm.com } 8087597Sminkyu.jeong@arm.com 8097597Sminkyu.jeong@arm.com void setPredicate(bool val) 8107597Sminkyu.jeong@arm.com { 8119046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8127600Sminkyu.jeong@arm.com 8137600Sminkyu.jeong@arm.com if (traceData) { 8147600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8157600Sminkyu.jeong@arm.com } 8167597Sminkyu.jeong@arm.com } 8177597Sminkyu.jeong@arm.com 8182702Sktlim@umich.edu /** Sets the ASID. */ 8192292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8202292SN/A 8212702Sktlim@umich.edu /** Sets the thread id. */ 8226221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8232292SN/A 8242731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8252702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8261060SN/A 8272731Sktlim@umich.edu /** Returns the thread context. */ 8282680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8291464SN/A 8301464SN/A public: 8311684SN/A /** Sets the effective address. */ 83210319SAndreas.Sandberg@ARM.com void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 8331684SN/A 8341684SN/A /** Returns the effective address. */ 83510319SAndreas.Sandberg@ARM.com Addr getEA() const { return instEffAddr; } 8361684SN/A 8371684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8389046SAli.Saidi@ARM.com bool doneEACalc() { return instFlags[EACalcDone]; } 8391684SN/A 8401684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8411464SN/A bool eaSrcsReady(); 8421681SN/A 84310824SAndreas.Sandberg@ARM.com /** Is this instruction's memory access strictly ordered? */ 84410824SAndreas.Sandberg@ARM.com bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8454032Sktlim@umich.edu 8464032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8479046SAli.Saidi@ARM.com bool hasRequest() { return instFlags[ReqMade]; } 8482292SN/A 8492292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8502292SN/A ListIt &getInstListIt() { return instListIt; } 8512292SN/A 8522292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8532292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8543326Sktlim@umich.edu 8553326Sktlim@umich.edu public: 8563326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 85710319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const 8583326Sktlim@umich.edu { return thread->storeCondFailures; } 8593326Sktlim@umich.edu 8603326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 86110319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int sc_failures) 8623326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 86310529Smorr@cs.wisc.edu 86410529Smorr@cs.wisc.edu public: 86510529Smorr@cs.wisc.edu // monitor/mwait funtions 86610529Smorr@cs.wisc.edu void armMonitor(Addr address) { cpu->armMonitor(address); } 86710529Smorr@cs.wisc.edu bool mwait(PacketPtr pkt) { return cpu->mwait(pkt); } 86810529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 86910529Smorr@cs.wisc.edu { return cpu->mwaitAtomic(tc, cpu->dtb); } 87010529Smorr@cs.wisc.edu AddressMonitor *getAddrMonitor() { return cpu->getCpuAddrMonitor(); } 8711060SN/A}; 8721060SN/A 8731060SN/Atemplate<class Impl> 8747520Sgblack@eecs.umich.eduFault 8758444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8768444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8771060SN/A{ 8789046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 8797944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8806974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8816974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8826974Stjones1@inf.ed.ac.uk 8839046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 8847944SGiacomo.Gabrielli@arm.com req = savedReq; 8857944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8867944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8877944SGiacomo.Gabrielli@arm.com } else { 8888832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 8897944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8904032Sktlim@umich.edu 89110024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 89210024Sdam.sunwoo@arm.com 8937944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8947944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8957944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8967944SGiacomo.Gabrielli@arm.com } 8977944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8981060SN/A } 8991060SN/A 9009046SAli.Saidi@ARM.com if (translationCompleted()) { 9017944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 9027944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 9038199SAli.Saidi@ARM.com effSize = size; 9049046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9058887Sgeoffrey.blake@arm.com 9068887Sgeoffrey.blake@arm.com if (cpu->checker) { 9078887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9088887Sgeoffrey.blake@arm.com delete reqToVerify; 9098887Sgeoffrey.blake@arm.com } 9108887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9118733Sgeoffrey.blake@arm.com } 9127944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9137944SGiacomo.Gabrielli@arm.com } else { 9147944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9157944SGiacomo.Gabrielli@arm.com // instruction as executed. 9167944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9177944SGiacomo.Gabrielli@arm.com } 9187944SGiacomo.Gabrielli@arm.com 9197944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 9207944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 9217944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 9227944SGiacomo.Gabrielli@arm.com if (data) 9237944SGiacomo.Gabrielli@arm.com bzero(data, size); 9247944SGiacomo.Gabrielli@arm.com } 9257577SAli.Saidi@ARM.com } 9267577SAli.Saidi@ARM.com 92710665SAli.Saidi@ARM.com if (traceData) 92810665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9291060SN/A 9301060SN/A return fault; 9311060SN/A} 9321060SN/A 9331060SN/Atemplate<class Impl> 9347520Sgblack@eecs.umich.eduFault 9358444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 9368444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9371060SN/A{ 93810665SAli.Saidi@ARM.com if (traceData) 93910665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9401060SN/A 9419046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 9427944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9436974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9446974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9456974Stjones1@inf.ed.ac.uk 9469046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9477944SGiacomo.Gabrielli@arm.com req = savedReq; 9487944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9497944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9507944SGiacomo.Gabrielli@arm.com } else { 9518832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9527944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9537944SGiacomo.Gabrielli@arm.com 95410024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 95510024Sdam.sunwoo@arm.com 9567944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9577944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9587944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9597944SGiacomo.Gabrielli@arm.com } 9607944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9616974Stjones1@inf.ed.ac.uk } 9624032Sktlim@umich.edu 9639046SAli.Saidi@ARM.com if (fault == NoFault && translationCompleted()) { 9642678Sktlim@umich.edu effAddr = req->getVaddr(); 9658199SAli.Saidi@ARM.com effSize = size; 9669046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9678887Sgeoffrey.blake@arm.com 9688887Sgeoffrey.blake@arm.com if (cpu->checker) { 9698887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9708887Sgeoffrey.blake@arm.com delete reqToVerify; 9718887Sgeoffrey.blake@arm.com } 9728887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9738733Sgeoffrey.blake@arm.com } 9746975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9751060SN/A } 9761060SN/A 9771060SN/A return fault; 9781060SN/A} 9791060SN/A 9806973Stjones1@inf.ed.ac.uktemplate<class Impl> 9816973Stjones1@inf.ed.ac.ukinline void 9826974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9836974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9846974Stjones1@inf.ed.ac.uk{ 9856974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9869814Sandreas.hansson@arm.com unsigned block_size = cpu->cacheLineSize(); 9876974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9886974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9896974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9906974Stjones1@inf.ed.ac.uk 9916974Stjones1@inf.ed.ac.uk // Spans two blocks. 9926974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9936974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9946974Stjones1@inf.ed.ac.uk } 9956974Stjones1@inf.ed.ac.uk} 9966974Stjones1@inf.ed.ac.uk 9976974Stjones1@inf.ed.ac.uktemplate<class Impl> 9986974Stjones1@inf.ed.ac.ukinline void 9996974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10006974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10016973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10026973Stjones1@inf.ed.ac.uk{ 10039046SAli.Saidi@ARM.com translationStarted(true); 10047944SGiacomo.Gabrielli@arm.com 10056974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10066974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10076974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10086974Stjones1@inf.ed.ac.uk 10096974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10108486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10118486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10129932SAli.Saidi@ARM.com 10136974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10149932SAli.Saidi@ARM.com 10159046SAli.Saidi@ARM.com if (!translationCompleted()) { 10169932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10179932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10189932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10199932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10209932SAli.Saidi@ARM.com fault = NoFault; 10219932SAli.Saidi@ARM.com 10227944SGiacomo.Gabrielli@arm.com // Save memory requests. 10237944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10247944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10257944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10267944SGiacomo.Gabrielli@arm.com } 10276974Stjones1@inf.ed.ac.uk } else { 10286974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10296974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10306974Stjones1@inf.ed.ac.uk 10316974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10328486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10338486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10348486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10358486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10366974Stjones1@inf.ed.ac.uk 10376974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10386974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10399932SAli.Saidi@ARM.com 10409046SAli.Saidi@ARM.com if (!translationCompleted()) { 10419932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10429932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10439932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10449932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10459932SAli.Saidi@ARM.com fault = NoFault; 10469932SAli.Saidi@ARM.com 10477944SGiacomo.Gabrielli@arm.com // Save memory requests. 10487944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10497944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10507944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10517944SGiacomo.Gabrielli@arm.com } 10526974Stjones1@inf.ed.ac.uk } 10536973Stjones1@inf.ed.ac.uk} 10546973Stjones1@inf.ed.ac.uk 10556973Stjones1@inf.ed.ac.uktemplate<class Impl> 10566973Stjones1@inf.ed.ac.ukinline void 10576973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10586973Stjones1@inf.ed.ac.uk{ 10596973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10606973Stjones1@inf.ed.ac.uk 106110824SAndreas.Sandberg@ARM.com instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 10626973Stjones1@inf.ed.ac.uk 10636973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 106411097Songal@cs.wisc.edu // save Paddr for a single req 106511097Songal@cs.wisc.edu physEffAddrLow = state->getPaddr(); 106611097Songal@cs.wisc.edu 106711097Songal@cs.wisc.edu // case for the request that has been split 106811097Songal@cs.wisc.edu if (state->isSplit) { 106911097Songal@cs.wisc.edu physEffAddrLow = state->sreqLow->getPaddr(); 107011097Songal@cs.wisc.edu physEffAddrHigh = state->sreqHigh->getPaddr(); 107111097Songal@cs.wisc.edu } 107211097Songal@cs.wisc.edu 10736973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10746973Stjones1@inf.ed.ac.uk 10756973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10766973Stjones1@inf.ed.ac.uk assert(state->res); 10776973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10786973Stjones1@inf.ed.ac.uk } 10796973Stjones1@inf.ed.ac.uk 10806973Stjones1@inf.ed.ac.uk } else { 10816973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10826973Stjones1@inf.ed.ac.uk } 10836973Stjones1@inf.ed.ac.uk delete state; 10847944SGiacomo.Gabrielli@arm.com 10859046SAli.Saidi@ARM.com translationCompleted(true); 10866973Stjones1@inf.ed.ac.uk} 10876973Stjones1@inf.ed.ac.uk 10881464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1089