base_dyn_inst.hh revision 10715
1298SN/A/* 22188SN/A * Copyright (c) 2011,2013 ARM Limited 3298SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 4298SN/A * All rights reserved. 5298SN/A * 6298SN/A * The license below extends only to copyright in the software and shall 7298SN/A * not be construed as granting a license to any other intellectual 8298SN/A * property including but not limited to intellectual property relating 9298SN/A * to a hardware implementation of the functionality of the software 10298SN/A * licensed hereunder. You may use the software subject to the license 11298SN/A * terms below provided that you ensure that this notice is replicated 12298SN/A * unmodified and in its entirety in all distributions of the software, 13298SN/A * modified or unmodified, in source code or in binary form. 14298SN/A * 15298SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 16298SN/A * Copyright (c) 2009 The University of Edinburgh 17298SN/A * All rights reserved. 18298SN/A * 19298SN/A * Redistribution and use in source and binary forms, with or without 20298SN/A * modification, are permitted provided that the following conditions are 21298SN/A * met: redistributions of source code must retain the above copyright 22298SN/A * notice, this list of conditions and the following disclaimer; 23298SN/A * redistributions in binary form must reproduce the above copyright 24298SN/A * notice, this list of conditions and the following disclaimer in the 25298SN/A * documentation and/or other materials provided with the distribution; 26298SN/A * neither the name of the copyright holders nor the names of its 272665Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 282665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 29298SN/A * 30298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311642SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32954SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33956SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34956SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 354078Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36299SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37299SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382170SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 393089Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401717SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412680Sktlim@umich.edu * 422313SN/A * Authors: Kevin Lim 433565Sgblack@eecs.umich.edu * Timothy M. Jones 443565Sgblack@eecs.umich.edu */ 45298SN/A 46298SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 47695SN/A#define __CPU_BASE_DYN_INST_HH__ 48695SN/A 49954SN/A#include <bitset> 501052SN/A#include <list> 512080SN/A#include <string> 52298SN/A#include <queue> 53299SN/A 541052SN/A#include "arch/generic/tlb.hh" 55729SN/A#include "arch/utility.hh" 562107SN/A#include "base/trace.hh" 57298SN/A#include "config/the_isa.hh" 585504Snate@binkert.org#include "cpu/checker/cpu.hh" 595504Snate@binkert.org#include "cpu/o3/comm.hh" 605504Snate@binkert.org#include "cpu/exec_context.hh" 615504Snate@binkert.org#include "cpu/exetrace.hh" 62298SN/A#include "cpu/inst_seq.hh" 635504Snate@binkert.org#include "cpu/op_class.hh" 645504Snate@binkert.org#include "cpu/static_inst.hh" 655504Snate@binkert.org#include "cpu/translation.hh" 665504Snate@binkert.org#include "mem/packet.hh" 675504Snate@binkert.org#include "sim/byteswap.hh" 685504Snate@binkert.org#include "sim/system.hh" 695504Snate@binkert.org 705504Snate@binkert.org/** 715504Snate@binkert.org * @file 725504Snate@binkert.org * Defines a dynamic instruction context. 735504Snate@binkert.org */ 745504Snate@binkert.org 755504Snate@binkert.orgtemplate <class Impl> 765504Snate@binkert.orgclass BaseDynInst : public ExecContext, public RefCounted 775504Snate@binkert.org{ 785504Snate@binkert.org public: 795504Snate@binkert.org // Typedef for the CPU. 805504Snate@binkert.org typedef typename Impl::CPUType ImplCPU; 815504Snate@binkert.org typedef typename ImplCPU::ImplState ImplState; 825504Snate@binkert.org 835504Snate@binkert.org // Logical register index type. 845504Snate@binkert.org typedef TheISA::RegIndex RegIndex; 855504Snate@binkert.org 865504Snate@binkert.org // The DynInstPtr type. 875504Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 885504Snate@binkert.org typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 895504Snate@binkert.org 905504Snate@binkert.org // The list of instructions iterator type. 915504Snate@binkert.org typedef typename std::list<DynInstPtr>::iterator ListIt; 925504Snate@binkert.org 935504Snate@binkert.org enum { 945504Snate@binkert.org MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 955504Snate@binkert.org MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 965504Snate@binkert.org }; 975504Snate@binkert.org 985504Snate@binkert.org union Result { 995504Snate@binkert.org uint64_t integer; 1005504Snate@binkert.org double dbl; 1015504Snate@binkert.org void set(uint64_t i) { integer = i; } 1025504Snate@binkert.org void set(double d) { dbl = d; } 1035504Snate@binkert.org void get(uint64_t& i) { i = integer; } 1045504Snate@binkert.org void get(double& d) { d = dbl; } 1055504Snate@binkert.org }; 1065504Snate@binkert.org 1075504Snate@binkert.org protected: 1085504Snate@binkert.org enum Status { 1095504Snate@binkert.org IqEntry, /// Instruction is in the IQ 1105504Snate@binkert.org RobEntry, /// Instruction is in the ROB 1115504Snate@binkert.org LsqEntry, /// Instruction is in the LSQ 1125504Snate@binkert.org Completed, /// Instruction has completed 1135504Snate@binkert.org ResultReady, /// Instruction has its result 1145504Snate@binkert.org CanIssue, /// Instruction can issue and execute 1155504Snate@binkert.org Issued, /// Instruction has issued 1165504Snate@binkert.org Executed, /// Instruction has executed 1175504Snate@binkert.org CanCommit, /// Instruction can commit 1185504Snate@binkert.org AtCommit, /// Instruction has reached commit 1195504Snate@binkert.org Committed, /// Instruction has committed 1205504Snate@binkert.org Squashed, /// Instruction is squashed 1215504Snate@binkert.org SquashedInIQ, /// Instruction is squashed in the IQ 1225504Snate@binkert.org SquashedInLSQ, /// Instruction is squashed in the LSQ 1235504Snate@binkert.org SquashedInROB, /// Instruction is squashed in the ROB 1245504Snate@binkert.org RecoverInst, /// Is a recover instruction 1255504Snate@binkert.org BlockingInst, /// Is a blocking instruction 1265504Snate@binkert.org ThreadsyncWait, /// Is a thread synchronization instruction 1275504Snate@binkert.org SerializeBefore, /// Needs to serialize on 1285504Snate@binkert.org /// instructions ahead of it 1295504Snate@binkert.org SerializeAfter, /// Needs to serialize instructions behind it 1305504Snate@binkert.org SerializeHandled, /// Serialization has been handled 1315504Snate@binkert.org NumStatus 1325504Snate@binkert.org }; 1335504Snate@binkert.org 1345504Snate@binkert.org enum Flags { 1355504Snate@binkert.org TranslationStarted, 1365504Snate@binkert.org TranslationCompleted, 1375504Snate@binkert.org PossibleLoadViolation, 1385504Snate@binkert.org HitExternalSnoop, 1395504Snate@binkert.org EffAddrValid, 1405504Snate@binkert.org RecordResult, 1415504Snate@binkert.org Predicate, 1425504Snate@binkert.org PredTaken, 1435504Snate@binkert.org /** Whether or not the effective address calculation is completed. 1445504Snate@binkert.org * @todo: Consider if this is necessary or not. 145711SN/A */ 146711SN/A EACalcDone, 1475504Snate@binkert.org IsUncacheable, 1485504Snate@binkert.org ReqMade, 149310SN/A MemOpDone, 1505504Snate@binkert.org MaxFlags 1515504Snate@binkert.org }; 1523373Sstever@eecs.umich.edu 1535504Snate@binkert.org public: 1545504Snate@binkert.org /** The sequence number of the instruction. */ 1555504Snate@binkert.org InstSeqNum seqNum; 1565504Snate@binkert.org 1575504Snate@binkert.org /** The StaticInst used by this BaseDynInst. */ 1585504Snate@binkert.org const StaticInstPtr staticInst; 1595504Snate@binkert.org 1605504Snate@binkert.org /** Pointer to the Impl's CPU object. */ 1615504Snate@binkert.org ImplCPU *cpu; 1625504Snate@binkert.org 1635504Snate@binkert.org BaseCPU *getCpuPtr() { return cpu; } 1645504Snate@binkert.org 1655504Snate@binkert.org /** Pointer to the thread state. */ 1665504Snate@binkert.org ImplState *thread; 1675504Snate@binkert.org 1685504Snate@binkert.org /** The kind of fault this instruction has generated. */ 1695504Snate@binkert.org Fault fault; 1705504Snate@binkert.org 1715504Snate@binkert.org /** InstRecord that tracks this instructions. */ 1725504Snate@binkert.org Trace::InstRecord *traceData; 1735504Snate@binkert.org 1745504Snate@binkert.org protected: 1755504Snate@binkert.org /** The result of the instruction; assumes an instruction can have many 1765504Snate@binkert.org * destination registers. 1775504Snate@binkert.org */ 1785504Snate@binkert.org std::queue<Result> instResult; 1795504Snate@binkert.org 1805504Snate@binkert.org /** PC state for this instruction. */ 1815504Snate@binkert.org TheISA::PCState pc; 1825504Snate@binkert.org 1835504Snate@binkert.org /* An amalgamation of a lot of boolean values into one */ 1845504Snate@binkert.org std::bitset<MaxFlags> instFlags; 1855504Snate@binkert.org 1865504Snate@binkert.org /** The status of this BaseDynInst. Several bits can be set. */ 1875504Snate@binkert.org std::bitset<NumStatus> status; 1885504Snate@binkert.org 1895504Snate@binkert.org /** Whether or not the source register is ready. 1905504Snate@binkert.org * @todo: Not sure this should be here vs the derived class. 1915504Snate@binkert.org */ 1925504Snate@binkert.org std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1935504Snate@binkert.org 1945504Snate@binkert.org public: 1955504Snate@binkert.org /** The thread this instruction is from. */ 1965504Snate@binkert.org ThreadID threadNumber; 1975504Snate@binkert.org 1985504Snate@binkert.org /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1995504Snate@binkert.org ListIt instListIt; 2005504Snate@binkert.org 2015504Snate@binkert.org ////////////////////// Branch Data /////////////// 2025504Snate@binkert.org /** Predicted PC state after this instruction. */ 2035504Snate@binkert.org TheISA::PCState predPC; 2045504Snate@binkert.org 2055504Snate@binkert.org /** The Macroop if one exists */ 2065504Snate@binkert.org const StaticInstPtr macroop; 2075504Snate@binkert.org 2085504Snate@binkert.org /** How many source registers are ready. */ 2095504Snate@binkert.org uint8_t readyRegs; 2105504Snate@binkert.org 2115504Snate@binkert.org public: 2125504Snate@binkert.org /////////////////////// Load Store Data ////////////////////// 2135504Snate@binkert.org /** The effective virtual address (lds & stores only). */ 2145504Snate@binkert.org Addr effAddr; 2155504Snate@binkert.org 2165504Snate@binkert.org /** The effective physical address. */ 2175504Snate@binkert.org Addr physEffAddr; 2185504Snate@binkert.org 2195504Snate@binkert.org /** The memory request flags (from translation). */ 2205504Snate@binkert.org unsigned memReqFlags; 2215504Snate@binkert.org 2225504Snate@binkert.org /** data address space ID, for loads & stores. */ 2235504Snate@binkert.org short asid; 2245504Snate@binkert.org 2255504Snate@binkert.org /** The size of the request */ 2265504Snate@binkert.org uint8_t effSize; 2275504Snate@binkert.org 2285504Snate@binkert.org /** Pointer to the data for the memory access. */ 2295504Snate@binkert.org uint8_t *memData; 2305504Snate@binkert.org 2315504Snate@binkert.org /** Load queue index. */ 2325504Snate@binkert.org int16_t lqIdx; 2335504Snate@binkert.org 2345504Snate@binkert.org /** Store queue index. */ 2355504Snate@binkert.org int16_t sqIdx; 2365504Snate@binkert.org 2375504Snate@binkert.org 2385504Snate@binkert.org /////////////////////// TLB Miss ////////////////////// 2395504Snate@binkert.org /** 2405504Snate@binkert.org * Saved memory requests (needed when the DTB address translation is 2415504Snate@binkert.org * delayed due to a hw page table walk). 2425504Snate@binkert.org */ 2435504Snate@binkert.org RequestPtr savedReq; 2445504Snate@binkert.org RequestPtr savedSreqLow; 2455504Snate@binkert.org RequestPtr savedSreqHigh; 2465504Snate@binkert.org 2475504Snate@binkert.org /////////////////////// Checker ////////////////////// 2485504Snate@binkert.org // Need a copy of main request pointer to verify on writes. 2495504Snate@binkert.org RequestPtr reqToVerify; 2505504Snate@binkert.org 2515504Snate@binkert.org private: 2525504Snate@binkert.org /** Instruction effective address. 2535504Snate@binkert.org * @todo: Consider if this is necessary or not. 2545504Snate@binkert.org */ 2555504Snate@binkert.org Addr instEffAddr; 2565504Snate@binkert.org 2575504Snate@binkert.org protected: 2585504Snate@binkert.org /** Flattened register index of the destination registers of this 2595504Snate@binkert.org * instruction. 2605504Snate@binkert.org */ 2615504Snate@binkert.org TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2625504Snate@binkert.org 2635504Snate@binkert.org /** Physical register index of the destination registers of this 2645504Snate@binkert.org * instruction. 2655504Snate@binkert.org */ 2665504Snate@binkert.org PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2675504Snate@binkert.org 2685504Snate@binkert.org /** Physical register index of the source registers of this 2695504Snate@binkert.org * instruction. 2705504Snate@binkert.org */ 271310SN/A PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 272299SN/A 2735504Snate@binkert.org /** Physical register index of the previous producers of the 2742188SN/A * architected destinations. 2755504Snate@binkert.org */ 2765504Snate@binkert.org PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2775504Snate@binkert.org 2782235SN/A 2795504Snate@binkert.org public: 2805504Snate@binkert.org /** Records changes to result? */ 2813368Sstever@eecs.umich.edu void recordResult(bool f) { instFlags[RecordResult] = f; } 2825504Snate@binkert.org 2835504Snate@binkert.org /** Is the effective virtual address valid. */ 2845504Snate@binkert.org bool effAddrValid() const { return instFlags[EffAddrValid]; } 2855504Snate@binkert.org 2865504Snate@binkert.org /** Whether or not the memory operation is done. */ 2875504Snate@binkert.org bool memOpDone() const { return instFlags[MemOpDone]; } 2883368Sstever@eecs.umich.edu void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2895504Snate@binkert.org 2905504Snate@binkert.org 2915504Snate@binkert.org //////////////////////////////////////////// 2922188SN/A // 2932188SN/A // INSTRUCTION EXECUTION 2945504Snate@binkert.org // 2955504Snate@binkert.org //////////////////////////////////////////// 2965504Snate@binkert.org 2975504Snate@binkert.org void demapPage(Addr vaddr, uint64_t asn) 2985504Snate@binkert.org { 2992188SN/A cpu->demapPage(vaddr, asn); 3005504Snate@binkert.org } 3015504Snate@binkert.org void demapInstPage(Addr vaddr, uint64_t asn) 3025504Snate@binkert.org { 3035504Snate@binkert.org cpu->demapPage(vaddr, asn); 3045504Snate@binkert.org } 3052235SN/A void demapDataPage(Addr vaddr, uint64_t asn) 3065504Snate@binkert.org { 3075504Snate@binkert.org cpu->demapPage(vaddr, asn); 3085504Snate@binkert.org } 3095504Snate@binkert.org 3105504Snate@binkert.org Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3113368Sstever@eecs.umich.edu 3125504Snate@binkert.org Fault writeMem(uint8_t *data, unsigned size, 313 Addr addr, unsigned flags, uint64_t *res); 314 315 /** Splits a request in two if it crosses a dcache block. */ 316 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 317 RequestPtr &sreqHigh); 318 319 /** Initiate a DTB address translation. */ 320 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 321 RequestPtr sreqHigh, uint64_t *res, 322 BaseTLB::Mode mode); 323 324 /** Finish a DTB address translation. */ 325 void finishTranslation(WholeTranslationState *state); 326 327 /** True if the DTB address translation has started. */ 328 bool translationStarted() const { return instFlags[TranslationStarted]; } 329 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 330 331 /** True if the DTB address translation has completed. */ 332 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 333 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 334 335 /** True if this address was found to match a previous load and they issued 336 * out of order. If that happend, then it's only a problem if an incoming 337 * snoop invalidate modifies the line, in which case we need to squash. 338 * If nothing modified the line the order doesn't matter. 339 */ 340 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 341 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 342 343 /** True if the address hit a external snoop while sitting in the LSQ. 344 * If this is true and a older instruction sees it, this instruction must 345 * reexecute 346 */ 347 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 348 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 349 350 /** 351 * Returns true if the DTB address translation is being delayed due to a hw 352 * page table walk. 353 */ 354 bool isTranslationDelayed() const 355 { 356 return (translationStarted() && !translationCompleted()); 357 } 358 359 public: 360#ifdef DEBUG 361 void dumpSNList(); 362#endif 363 364 /** Returns the physical register index of the i'th destination 365 * register. 366 */ 367 PhysRegIndex renamedDestRegIdx(int idx) const 368 { 369 return _destRegIdx[idx]; 370 } 371 372 /** Returns the physical register index of the i'th source register. */ 373 PhysRegIndex renamedSrcRegIdx(int idx) const 374 { 375 assert(TheISA::MaxInstSrcRegs > idx); 376 return _srcRegIdx[idx]; 377 } 378 379 /** Returns the flattened register index of the i'th destination 380 * register. 381 */ 382 TheISA::RegIndex flattenedDestRegIdx(int idx) const 383 { 384 return _flatDestRegIdx[idx]; 385 } 386 387 /** Returns the physical register index of the previous physical register 388 * that remapped to the same logical register index. 389 */ 390 PhysRegIndex prevDestRegIdx(int idx) const 391 { 392 return _prevDestRegIdx[idx]; 393 } 394 395 /** Renames a destination register to a physical register. Also records 396 * the previous physical register that the logical register mapped to. 397 */ 398 void renameDestReg(int idx, 399 PhysRegIndex renamed_dest, 400 PhysRegIndex previous_rename) 401 { 402 _destRegIdx[idx] = renamed_dest; 403 _prevDestRegIdx[idx] = previous_rename; 404 } 405 406 /** Renames a source logical register to the physical register which 407 * has/will produce that logical register's result. 408 * @todo: add in whether or not the source register is ready. 409 */ 410 void renameSrcReg(int idx, PhysRegIndex renamed_src) 411 { 412 _srcRegIdx[idx] = renamed_src; 413 } 414 415 /** Flattens a destination architectural register index into a logical 416 * index. 417 */ 418 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 419 { 420 _flatDestRegIdx[idx] = flattened_dest; 421 } 422 /** BaseDynInst constructor given a binary instruction. 423 * @param staticInst A StaticInstPtr to the underlying instruction. 424 * @param pc The PC state for the instruction. 425 * @param predPC The predicted next PC state for the instruction. 426 * @param seq_num The sequence number of the instruction. 427 * @param cpu Pointer to the instruction's CPU. 428 */ 429 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 430 TheISA::PCState pc, TheISA::PCState predPC, 431 InstSeqNum seq_num, ImplCPU *cpu); 432 433 /** BaseDynInst constructor given a StaticInst pointer. 434 * @param _staticInst The StaticInst for this BaseDynInst. 435 */ 436 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 437 438 /** BaseDynInst destructor. */ 439 ~BaseDynInst(); 440 441 private: 442 /** Function to initialize variables in the constructors. */ 443 void initVars(); 444 445 public: 446 /** Dumps out contents of this BaseDynInst. */ 447 void dump(); 448 449 /** Dumps out contents of this BaseDynInst into given string. */ 450 void dump(std::string &outstring); 451 452 /** Read this CPU's ID. */ 453 int cpuId() const { return cpu->cpuId(); } 454 455 /** Read this CPU's Socket ID. */ 456 uint32_t socketId() const { return cpu->socketId(); } 457 458 /** Read this CPU's data requestor ID */ 459 MasterID masterId() const { return cpu->dataMasterId(); } 460 461 /** Read this context's system-wide ID **/ 462 int contextId() const { return thread->contextId(); } 463 464 /** Returns the fault type. */ 465 Fault getFault() const { return fault; } 466 467 /** Checks whether or not this instruction has had its branch target 468 * calculated yet. For now it is not utilized and is hacked to be 469 * always false. 470 * @todo: Actually use this instruction. 471 */ 472 bool doneTargCalc() { return false; } 473 474 /** Set the predicted target of this current instruction. */ 475 void setPredTarg(const TheISA::PCState &_predPC) 476 { 477 predPC = _predPC; 478 } 479 480 const TheISA::PCState &readPredTarg() { return predPC; } 481 482 /** Returns the predicted PC immediately after the branch. */ 483 Addr predInstAddr() { return predPC.instAddr(); } 484 485 /** Returns the predicted PC two instructions after the branch */ 486 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 487 488 /** Returns the predicted micro PC after the branch */ 489 Addr predMicroPC() { return predPC.microPC(); } 490 491 /** Returns whether the instruction was predicted taken or not. */ 492 bool readPredTaken() 493 { 494 return instFlags[PredTaken]; 495 } 496 497 void setPredTaken(bool predicted_taken) 498 { 499 instFlags[PredTaken] = predicted_taken; 500 } 501 502 /** Returns whether the instruction mispredicted. */ 503 bool mispredicted() 504 { 505 TheISA::PCState tempPC = pc; 506 TheISA::advancePC(tempPC, staticInst); 507 return !(tempPC == predPC); 508 } 509 510 // 511 // Instruction types. Forward checks to StaticInst object. 512 // 513 bool isNop() const { return staticInst->isNop(); } 514 bool isMemRef() const { return staticInst->isMemRef(); } 515 bool isLoad() const { return staticInst->isLoad(); } 516 bool isStore() const { return staticInst->isStore(); } 517 bool isStoreConditional() const 518 { return staticInst->isStoreConditional(); } 519 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 520 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 521 bool isInteger() const { return staticInst->isInteger(); } 522 bool isFloating() const { return staticInst->isFloating(); } 523 bool isControl() const { return staticInst->isControl(); } 524 bool isCall() const { return staticInst->isCall(); } 525 bool isReturn() const { return staticInst->isReturn(); } 526 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 527 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 528 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 529 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 530 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 531 bool isThreadSync() const { return staticInst->isThreadSync(); } 532 bool isSerializing() const { return staticInst->isSerializing(); } 533 bool isSerializeBefore() const 534 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 535 bool isSerializeAfter() const 536 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 537 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 538 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 539 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 540 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 541 bool isQuiesce() const { return staticInst->isQuiesce(); } 542 bool isIprAccess() const { return staticInst->isIprAccess(); } 543 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 544 bool isSyscall() const { return staticInst->isSyscall(); } 545 bool isMacroop() const { return staticInst->isMacroop(); } 546 bool isMicroop() const { return staticInst->isMicroop(); } 547 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 548 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 549 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 550 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 551 552 /** Temporarily sets this instruction as a serialize before instruction. */ 553 void setSerializeBefore() { status.set(SerializeBefore); } 554 555 /** Clears the serializeBefore part of this instruction. */ 556 void clearSerializeBefore() { status.reset(SerializeBefore); } 557 558 /** Checks if this serializeBefore is only temporarily set. */ 559 bool isTempSerializeBefore() { return status[SerializeBefore]; } 560 561 /** Temporarily sets this instruction as a serialize after instruction. */ 562 void setSerializeAfter() { status.set(SerializeAfter); } 563 564 /** Clears the serializeAfter part of this instruction.*/ 565 void clearSerializeAfter() { status.reset(SerializeAfter); } 566 567 /** Checks if this serializeAfter is only temporarily set. */ 568 bool isTempSerializeAfter() { return status[SerializeAfter]; } 569 570 /** Sets the serialization part of this instruction as handled. */ 571 void setSerializeHandled() { status.set(SerializeHandled); } 572 573 /** Checks if the serialization part of this instruction has been 574 * handled. This does not apply to the temporary serializing 575 * state; it only applies to this instruction's own permanent 576 * serializing state. 577 */ 578 bool isSerializeHandled() { return status[SerializeHandled]; } 579 580 /** Returns the opclass of this instruction. */ 581 OpClass opClass() const { return staticInst->opClass(); } 582 583 /** Returns the branch target address. */ 584 TheISA::PCState branchTarget() const 585 { return staticInst->branchTarget(pc); } 586 587 /** Returns the number of source registers. */ 588 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 589 590 /** Returns the number of destination registers. */ 591 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 592 593 // the following are used to track physical register usage 594 // for machines with separate int & FP reg files 595 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 596 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 597 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 598 599 /** Returns the logical register index of the i'th destination register. */ 600 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 601 602 /** Returns the logical register index of the i'th source register. */ 603 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 604 605 /** Pops a result off the instResult queue */ 606 template <class T> 607 void popResult(T& t) 608 { 609 if (!instResult.empty()) { 610 instResult.front().get(t); 611 instResult.pop(); 612 } 613 } 614 615 /** Read the most recent result stored by this instruction */ 616 template <class T> 617 void readResult(T& t) 618 { 619 instResult.back().get(t); 620 } 621 622 /** Pushes a result onto the instResult queue */ 623 template <class T> 624 void setResult(T t) 625 { 626 if (instFlags[RecordResult]) { 627 Result instRes; 628 instRes.set(t); 629 instResult.push(instRes); 630 } 631 } 632 633 /** Records an integer register being set to a value. */ 634 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 635 { 636 setResult<uint64_t>(val); 637 } 638 639 /** Records a CC register being set to a value. */ 640 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 641 { 642 setResult<uint64_t>(val); 643 } 644 645 /** Records an fp register being set to a value. */ 646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 647 { 648 setResult<double>(val); 649 } 650 651 /** Records an fp register being set to an integer value. */ 652 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 653 { 654 setResult<uint64_t>(val); 655 } 656 657 /** Records that one of the source registers is ready. */ 658 void markSrcRegReady(); 659 660 /** Marks a specific register as ready. */ 661 void markSrcRegReady(RegIndex src_idx); 662 663 /** Returns if a source register is ready. */ 664 bool isReadySrcRegIdx(int idx) const 665 { 666 return this->_readySrcRegIdx[idx]; 667 } 668 669 /** Sets this instruction as completed. */ 670 void setCompleted() { status.set(Completed); } 671 672 /** Returns whether or not this instruction is completed. */ 673 bool isCompleted() const { return status[Completed]; } 674 675 /** Marks the result as ready. */ 676 void setResultReady() { status.set(ResultReady); } 677 678 /** Returns whether or not the result is ready. */ 679 bool isResultReady() const { return status[ResultReady]; } 680 681 /** Sets this instruction as ready to issue. */ 682 void setCanIssue() { status.set(CanIssue); } 683 684 /** Returns whether or not this instruction is ready to issue. */ 685 bool readyToIssue() const { return status[CanIssue]; } 686 687 /** Clears this instruction being able to issue. */ 688 void clearCanIssue() { status.reset(CanIssue); } 689 690 /** Sets this instruction as issued from the IQ. */ 691 void setIssued() { status.set(Issued); } 692 693 /** Returns whether or not this instruction has issued. */ 694 bool isIssued() const { return status[Issued]; } 695 696 /** Clears this instruction as being issued. */ 697 void clearIssued() { status.reset(Issued); } 698 699 /** Sets this instruction as executed. */ 700 void setExecuted() { status.set(Executed); } 701 702 /** Returns whether or not this instruction has executed. */ 703 bool isExecuted() const { return status[Executed]; } 704 705 /** Sets this instruction as ready to commit. */ 706 void setCanCommit() { status.set(CanCommit); } 707 708 /** Clears this instruction as being ready to commit. */ 709 void clearCanCommit() { status.reset(CanCommit); } 710 711 /** Returns whether or not this instruction is ready to commit. */ 712 bool readyToCommit() const { return status[CanCommit]; } 713 714 void setAtCommit() { status.set(AtCommit); } 715 716 bool isAtCommit() { return status[AtCommit]; } 717 718 /** Sets this instruction as committed. */ 719 void setCommitted() { status.set(Committed); } 720 721 /** Returns whether or not this instruction is committed. */ 722 bool isCommitted() const { return status[Committed]; } 723 724 /** Sets this instruction as squashed. */ 725 void setSquashed() { status.set(Squashed); } 726 727 /** Returns whether or not this instruction is squashed. */ 728 bool isSquashed() const { return status[Squashed]; } 729 730 //Instruction Queue Entry 731 //----------------------- 732 /** Sets this instruction as a entry the IQ. */ 733 void setInIQ() { status.set(IqEntry); } 734 735 /** Sets this instruction as a entry the IQ. */ 736 void clearInIQ() { status.reset(IqEntry); } 737 738 /** Returns whether or not this instruction has issued. */ 739 bool isInIQ() const { return status[IqEntry]; } 740 741 /** Sets this instruction as squashed in the IQ. */ 742 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 743 744 /** Returns whether or not this instruction is squashed in the IQ. */ 745 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 746 747 748 //Load / Store Queue Functions 749 //----------------------- 750 /** Sets this instruction as a entry the LSQ. */ 751 void setInLSQ() { status.set(LsqEntry); } 752 753 /** Sets this instruction as a entry the LSQ. */ 754 void removeInLSQ() { status.reset(LsqEntry); } 755 756 /** Returns whether or not this instruction is in the LSQ. */ 757 bool isInLSQ() const { return status[LsqEntry]; } 758 759 /** Sets this instruction as squashed in the LSQ. */ 760 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 761 762 /** Returns whether or not this instruction is squashed in the LSQ. */ 763 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 764 765 766 //Reorder Buffer Functions 767 //----------------------- 768 /** Sets this instruction as a entry the ROB. */ 769 void setInROB() { status.set(RobEntry); } 770 771 /** Sets this instruction as a entry the ROB. */ 772 void clearInROB() { status.reset(RobEntry); } 773 774 /** Returns whether or not this instruction is in the ROB. */ 775 bool isInROB() const { return status[RobEntry]; } 776 777 /** Sets this instruction as squashed in the ROB. */ 778 void setSquashedInROB() { status.set(SquashedInROB); } 779 780 /** Returns whether or not this instruction is squashed in the ROB. */ 781 bool isSquashedInROB() const { return status[SquashedInROB]; } 782 783 /** Read the PC state of this instruction. */ 784 TheISA::PCState pcState() const { return pc; } 785 786 /** Set the PC state of this instruction. */ 787 void pcState(const TheISA::PCState &val) { pc = val; } 788 789 /** Read the PC of this instruction. */ 790 const Addr instAddr() const { return pc.instAddr(); } 791 792 /** Read the PC of the next instruction. */ 793 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 794 795 /**Read the micro PC of this instruction. */ 796 const Addr microPC() const { return pc.microPC(); } 797 798 bool readPredicate() 799 { 800 return instFlags[Predicate]; 801 } 802 803 void setPredicate(bool val) 804 { 805 instFlags[Predicate] = val; 806 807 if (traceData) { 808 traceData->setPredicate(val); 809 } 810 } 811 812 /** Sets the ASID. */ 813 void setASID(short addr_space_id) { asid = addr_space_id; } 814 815 /** Sets the thread id. */ 816 void setTid(ThreadID tid) { threadNumber = tid; } 817 818 /** Sets the pointer to the thread state. */ 819 void setThreadState(ImplState *state) { thread = state; } 820 821 /** Returns the thread context. */ 822 ThreadContext *tcBase() { return thread->getTC(); } 823 824 public: 825 /** Sets the effective address. */ 826 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 827 828 /** Returns the effective address. */ 829 Addr getEA() const { return instEffAddr; } 830 831 /** Returns whether or not the eff. addr. calculation has been completed. */ 832 bool doneEACalc() { return instFlags[EACalcDone]; } 833 834 /** Returns whether or not the eff. addr. source registers are ready. */ 835 bool eaSrcsReady(); 836 837 /** Is this instruction's memory access uncacheable. */ 838 bool uncacheable() { return instFlags[IsUncacheable]; } 839 840 /** Has this instruction generated a memory request. */ 841 bool hasRequest() { return instFlags[ReqMade]; } 842 843 /** Returns iterator to this instruction in the list of all insts. */ 844 ListIt &getInstListIt() { return instListIt; } 845 846 /** Sets iterator for this instruction in the list of all insts. */ 847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 848 849 public: 850 /** Returns the number of consecutive store conditional failures. */ 851 unsigned int readStCondFailures() const 852 { return thread->storeCondFailures; } 853 854 /** Sets the number of consecutive store conditional failures. */ 855 void setStCondFailures(unsigned int sc_failures) 856 { thread->storeCondFailures = sc_failures; } 857 858 public: 859 // monitor/mwait funtions 860 void armMonitor(Addr address) { cpu->armMonitor(address); } 861 bool mwait(PacketPtr pkt) { return cpu->mwait(pkt); } 862 void mwaitAtomic(ThreadContext *tc) 863 { return cpu->mwaitAtomic(tc, cpu->dtb); } 864 AddressMonitor *getAddrMonitor() { return cpu->getCpuAddrMonitor(); } 865}; 866 867template<class Impl> 868Fault 869BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 870 unsigned size, unsigned flags) 871{ 872 instFlags[ReqMade] = true; 873 Request *req = NULL; 874 Request *sreqLow = NULL; 875 Request *sreqHigh = NULL; 876 877 if (instFlags[ReqMade] && translationStarted()) { 878 req = savedReq; 879 sreqLow = savedSreqLow; 880 sreqHigh = savedSreqHigh; 881 } else { 882 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 883 thread->contextId(), threadNumber); 884 885 req->taskId(cpu->taskId()); 886 887 // Only split the request if the ISA supports unaligned accesses. 888 if (TheISA::HasUnalignedMemAcc) { 889 splitRequest(req, sreqLow, sreqHigh); 890 } 891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 892 } 893 894 if (translationCompleted()) { 895 if (fault == NoFault) { 896 effAddr = req->getVaddr(); 897 effSize = size; 898 instFlags[EffAddrValid] = true; 899 900 if (cpu->checker) { 901 if (reqToVerify != NULL) { 902 delete reqToVerify; 903 } 904 reqToVerify = new Request(*req); 905 } 906 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 907 } else { 908 // Commit will have to clean up whatever happened. Set this 909 // instruction as executed. 910 this->setExecuted(); 911 } 912 913 if (fault != NoFault) { 914 // Return a fixed value to keep simulation deterministic even 915 // along misspeculated paths. 916 if (data) 917 bzero(data, size); 918 } 919 } 920 921 if (traceData) 922 traceData->setMem(addr, size, flags); 923 924 return fault; 925} 926 927template<class Impl> 928Fault 929BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 930 Addr addr, unsigned flags, uint64_t *res) 931{ 932 if (traceData) 933 traceData->setMem(addr, size, flags); 934 935 instFlags[ReqMade] = true; 936 Request *req = NULL; 937 Request *sreqLow = NULL; 938 Request *sreqHigh = NULL; 939 940 if (instFlags[ReqMade] && translationStarted()) { 941 req = savedReq; 942 sreqLow = savedSreqLow; 943 sreqHigh = savedSreqHigh; 944 } else { 945 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 946 thread->contextId(), threadNumber); 947 948 req->taskId(cpu->taskId()); 949 950 // Only split the request if the ISA supports unaligned accesses. 951 if (TheISA::HasUnalignedMemAcc) { 952 splitRequest(req, sreqLow, sreqHigh); 953 } 954 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 955 } 956 957 if (fault == NoFault && translationCompleted()) { 958 effAddr = req->getVaddr(); 959 effSize = size; 960 instFlags[EffAddrValid] = true; 961 962 if (cpu->checker) { 963 if (reqToVerify != NULL) { 964 delete reqToVerify; 965 } 966 reqToVerify = new Request(*req); 967 } 968 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 969 } 970 971 return fault; 972} 973 974template<class Impl> 975inline void 976BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 977 RequestPtr &sreqHigh) 978{ 979 // Check to see if the request crosses the next level block boundary. 980 unsigned block_size = cpu->cacheLineSize(); 981 Addr addr = req->getVaddr(); 982 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 983 assert(split_addr <= addr || split_addr - addr < block_size); 984 985 // Spans two blocks. 986 if (split_addr > addr) { 987 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 988 } 989} 990 991template<class Impl> 992inline void 993BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 994 RequestPtr sreqHigh, uint64_t *res, 995 BaseTLB::Mode mode) 996{ 997 translationStarted(true); 998 999 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 1000 WholeTranslationState *state = 1001 new WholeTranslationState(req, NULL, res, mode); 1002 1003 // One translation if the request isn't split. 1004 DataTranslation<BaseDynInstPtr> *trans = 1005 new DataTranslation<BaseDynInstPtr>(this, state); 1006 1007 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1008 1009 if (!translationCompleted()) { 1010 // The translation isn't yet complete, so we can't possibly have a 1011 // fault. Overwrite any existing fault we might have from a previous 1012 // execution of this instruction (e.g. an uncachable load that 1013 // couldn't execute because it wasn't at the head of the ROB). 1014 fault = NoFault; 1015 1016 // Save memory requests. 1017 savedReq = state->mainReq; 1018 savedSreqLow = state->sreqLow; 1019 savedSreqHigh = state->sreqHigh; 1020 } 1021 } else { 1022 WholeTranslationState *state = 1023 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1024 1025 // Two translations when the request is split. 1026 DataTranslation<BaseDynInstPtr> *stransLow = 1027 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1028 DataTranslation<BaseDynInstPtr> *stransHigh = 1029 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1030 1031 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1032 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1033 1034 if (!translationCompleted()) { 1035 // The translation isn't yet complete, so we can't possibly have a 1036 // fault. Overwrite any existing fault we might have from a previous 1037 // execution of this instruction (e.g. an uncachable load that 1038 // couldn't execute because it wasn't at the head of the ROB). 1039 fault = NoFault; 1040 1041 // Save memory requests. 1042 savedReq = state->mainReq; 1043 savedSreqLow = state->sreqLow; 1044 savedSreqHigh = state->sreqHigh; 1045 } 1046 } 1047} 1048 1049template<class Impl> 1050inline void 1051BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1052{ 1053 fault = state->getFault(); 1054 1055 instFlags[IsUncacheable] = state->isUncacheable(); 1056 1057 if (fault == NoFault) { 1058 physEffAddr = state->getPaddr(); 1059 memReqFlags = state->getFlags(); 1060 1061 if (state->mainReq->isCondSwap()) { 1062 assert(state->res); 1063 state->mainReq->setExtraData(*state->res); 1064 } 1065 1066 } else { 1067 state->deleteReqs(); 1068 } 1069 delete state; 1070 1071 translationCompleted(true); 1072} 1073 1074#endif // __CPU_BASE_DYN_INST_HH__ 1075