base.hh revision 9180
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#ifndef __CPU_BASE_HH__ 47#define __CPU_BASE_HH__ 48 49#include <vector> 50 51#include "arch/interrupts.hh" 52#include "arch/isa_traits.hh" 53#include "arch/microcode_rom.hh" 54#include "base/statistics.hh" 55#include "config/the_isa.hh" 56#include "mem/mem_object.hh" 57#include "sim/eventq.hh" 58#include "sim/full_system.hh" 59#include "sim/insttracer.hh" 60 61struct BaseCPUParams; 62class BranchPred; 63class CheckerCPU; 64class ThreadContext; 65class System; 66 67class CPUProgressEvent : public Event 68{ 69 protected: 70 Tick _interval; 71 Counter lastNumInst; 72 BaseCPU *cpu; 73 bool _repeatEvent; 74 75 public: 76 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 77 78 void process(); 79 80 void interval(Tick ival) { _interval = ival; } 81 Tick interval() { return _interval; } 82 83 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 84 85 virtual const char *description() const; 86}; 87 88class BaseCPU : public MemObject 89{ 90 protected: 91 92 // @todo remove me after debugging with legion done 93 Tick instCnt; 94 // every cpu has an id, put it in the base cpu 95 // Set at initialization, only time a cpuId might change is during a 96 // takeover (which should be done from within the BaseCPU anyway, 97 // therefore no setCpuId() method is provided 98 int _cpuId; 99 100 /** instruction side request id that must be placed in all requests */ 101 MasterID _instMasterId; 102 103 /** data side request id that must be placed in all requests */ 104 MasterID _dataMasterId; 105 106 /** 107 * Define a base class for the CPU ports (instruction and data) 108 * that is refined in the subclasses. This class handles the 109 * common cases, i.e. the functional accesses and the status 110 * changes and address range queries. The default behaviour for 111 * both atomic and timing access is to panic and the corresponding 112 * subclasses have to override these methods. 113 */ 114 class CpuPort : public MasterPort 115 { 116 public: 117 118 /** 119 * Create a CPU port with a name and a structural owner. 120 * 121 * @param _name port name including the owner 122 * @param _name structural owner of this port 123 */ 124 CpuPort(const std::string& _name, MemObject* _owner) : 125 MasterPort(_name, _owner) 126 { } 127 128 protected: 129 130 virtual bool recvTimingResp(PacketPtr pkt); 131 132 virtual void recvRetry(); 133 134 virtual void recvFunctionalSnoop(PacketPtr pkt); 135 136 }; 137 138 public: 139 140 /** 141 * Purely virtual method that returns a reference to the data 142 * port. All subclasses must implement this method. 143 * 144 * @return a reference to the data port 145 */ 146 virtual CpuPort &getDataPort() = 0; 147 148 /** 149 * Purely virtual method that returns a reference to the instruction 150 * port. All subclasses must implement this method. 151 * 152 * @return a reference to the instruction port 153 */ 154 virtual CpuPort &getInstPort() = 0; 155 156 /** Reads this CPU's ID. */ 157 int cpuId() { return _cpuId; } 158 159 /** Reads this CPU's unique data requestor ID */ 160 MasterID dataMasterId() { return _dataMasterId; } 161 /** Reads this CPU's unique instruction requestor ID */ 162 MasterID instMasterId() { return _instMasterId; } 163 164 /** 165 * Get a master port on this CPU. All CPUs have a data and 166 * instruction port, and this method uses getDataPort and 167 * getInstPort of the subclasses to resolve the two ports. 168 * 169 * @param if_name the port name 170 * @param idx ignored index 171 * 172 * @return a reference to the port with the given name 173 */ 174 MasterPort &getMasterPort(const std::string &if_name, int idx = -1); 175 176 inline void workItemBegin() { numWorkItemsStarted++; } 177 inline void workItemEnd() { numWorkItemsCompleted++; } 178 // @todo remove me after debugging with legion done 179 Tick instCount() { return instCnt; } 180 181 TheISA::MicrocodeRom microcodeRom; 182 183 protected: 184 TheISA::Interrupts *interrupts; 185 186 public: 187 TheISA::Interrupts * 188 getInterruptController() 189 { 190 return interrupts; 191 } 192 193 virtual void wakeup() = 0; 194 195 void 196 postInterrupt(int int_num, int index) 197 { 198 interrupts->post(int_num, index); 199 if (FullSystem) 200 wakeup(); 201 } 202 203 void 204 clearInterrupt(int int_num, int index) 205 { 206 interrupts->clear(int_num, index); 207 } 208 209 void 210 clearInterrupts() 211 { 212 interrupts->clearAll(); 213 } 214 215 bool 216 checkInterrupts(ThreadContext *tc) const 217 { 218 return FullSystem && interrupts->checkInterrupts(tc); 219 } 220 221 class ProfileEvent : public Event 222 { 223 private: 224 BaseCPU *cpu; 225 Tick interval; 226 227 public: 228 ProfileEvent(BaseCPU *cpu, Tick interval); 229 void process(); 230 }; 231 ProfileEvent *profileEvent; 232 233 protected: 234 std::vector<ThreadContext *> threadContexts; 235 236 Trace::InstTracer * tracer; 237 238 public: 239 240 // Mask to align PCs to MachInst sized boundaries 241 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 242 243 /// Provide access to the tracer pointer 244 Trace::InstTracer * getTracer() { return tracer; } 245 246 /// Notify the CPU that the indicated context is now active. The 247 /// delay parameter indicates the number of ticks to wait before 248 /// executing (typically 0 or 1). 249 virtual void activateContext(ThreadID thread_num, Cycles delay) {} 250 251 /// Notify the CPU that the indicated context is now suspended. 252 virtual void suspendContext(ThreadID thread_num) {} 253 254 /// Notify the CPU that the indicated context is now deallocated. 255 virtual void deallocateContext(ThreadID thread_num) {} 256 257 /// Notify the CPU that the indicated context is now halted. 258 virtual void haltContext(ThreadID thread_num) {} 259 260 /// Given a Thread Context pointer return the thread num 261 int findContext(ThreadContext *tc); 262 263 /// Given a thread num get tho thread context for it 264 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 265 266 public: 267 typedef BaseCPUParams Params; 268 const Params *params() const 269 { return reinterpret_cast<const Params *>(_params); } 270 BaseCPU(Params *params, bool is_checker = false); 271 virtual ~BaseCPU(); 272 273 virtual void init(); 274 virtual void startup(); 275 virtual void regStats(); 276 277 virtual void activateWhenReady(ThreadID tid) {}; 278 279 void registerThreadContexts(); 280 281 /// Prepare for another CPU to take over execution. When it is 282 /// is ready (drained pipe) it signals the sampler. 283 virtual void switchOut(); 284 285 /// Take over execution from the given CPU. Used for warm-up and 286 /// sampling. 287 virtual void takeOverFrom(BaseCPU *); 288 289 /** 290 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 291 * This is a constant for the duration of the simulation. 292 */ 293 ThreadID numThreads; 294 295 /** 296 * Vector of per-thread instruction-based event queues. Used for 297 * scheduling events based on number of instructions committed by 298 * a particular thread. 299 */ 300 EventQueue **comInstEventQueue; 301 302 /** 303 * Vector of per-thread load-based event queues. Used for 304 * scheduling events based on number of loads committed by 305 *a particular thread. 306 */ 307 EventQueue **comLoadEventQueue; 308 309 System *system; 310 311 /** 312 * Serialize this object to the given output stream. 313 * @param os The stream to serialize to. 314 */ 315 virtual void serialize(std::ostream &os); 316 317 /** 318 * Reconstruct the state of this object from a checkpoint. 319 * @param cp The checkpoint use. 320 * @param section The section name of this object 321 */ 322 virtual void unserialize(Checkpoint *cp, const std::string §ion); 323 324 /** 325 * Return pointer to CPU's branch predictor (NULL if none). 326 * @return Branch predictor pointer. 327 */ 328 virtual BranchPred *getBranchPred() { return NULL; }; 329 330 virtual Counter totalInsts() const = 0; 331 332 virtual Counter totalOps() const = 0; 333 334 // Function tracing 335 private: 336 bool functionTracingEnabled; 337 std::ostream *functionTraceStream; 338 Addr currentFunctionStart; 339 Addr currentFunctionEnd; 340 Tick functionEntryTick; 341 void enableFunctionTrace(); 342 void traceFunctionsInternal(Addr pc); 343 344 private: 345 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 346 347 public: 348 void traceFunctions(Addr pc) 349 { 350 if (functionTracingEnabled) 351 traceFunctionsInternal(pc); 352 } 353 354 static int numSimulatedCPUs() { return cpuList.size(); } 355 static Counter numSimulatedInsts() 356 { 357 Counter total = 0; 358 359 int size = cpuList.size(); 360 for (int i = 0; i < size; ++i) 361 total += cpuList[i]->totalInsts(); 362 363 return total; 364 } 365 366 static Counter numSimulatedOps() 367 { 368 Counter total = 0; 369 370 int size = cpuList.size(); 371 for (int i = 0; i < size; ++i) 372 total += cpuList[i]->totalOps(); 373 374 return total; 375 } 376 377 public: 378 // Number of CPU cycles simulated 379 Stats::Scalar numCycles; 380 Stats::Scalar numWorkItemsStarted; 381 Stats::Scalar numWorkItemsCompleted; 382}; 383 384#endif // __CPU_BASE_HH__ 385