base.hh revision 7823:dac01f14f20f
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "arch/microcode_rom.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "config/the_isa.hh"
42#include "sim/eventq.hh"
43#include "sim/insttracer.hh"
44#include "mem/mem_object.hh"
45
46#if FULL_SYSTEM
47#include "arch/interrupts.hh"
48#endif
49
50class BaseCPUParams;
51class BranchPred;
52class CheckerCPU;
53class ThreadContext;
54class System;
55class Port;
56
57namespace TheISA
58{
59    class Predecoder;
60}
61
62class CPUProgressEvent : public Event
63{
64  protected:
65    Tick _interval;
66    Counter lastNumInst;
67    BaseCPU *cpu;
68    bool _repeatEvent;
69
70  public:
71    CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
72
73    void process();
74
75    void interval(Tick ival) { _interval = ival; }
76    Tick interval() { return _interval; }
77
78    void repeatEvent(bool repeat) { _repeatEvent = repeat; }
79
80    virtual const char *description() const;
81};
82
83class BaseCPU : public MemObject
84{
85  protected:
86    // CPU's clock period in terms of the number of ticks of curTime.
87    Tick clock;
88    // @todo remove me after debugging with legion done
89    Tick instCnt;
90    // every cpu has an id, put it in the base cpu
91    // Set at initialization, only time a cpuId might change is during a
92    // takeover (which should be done from within the BaseCPU anyway,
93    // therefore no setCpuId() method is provided
94    int _cpuId;
95
96  public:
97    /** Reads this CPU's ID. */
98    int cpuId() { return _cpuId; }
99
100//    Tick currentTick;
101    inline Tick frequency() const { return SimClock::Frequency / clock; }
102    inline Tick ticks(int numCycles) const { return clock * numCycles; }
103    inline Tick curCycle() const { return curTick() / clock; }
104    inline Tick tickToCycles(Tick val) const { return val / clock; }
105    // @todo remove me after debugging with legion done
106    Tick instCount() { return instCnt; }
107
108    /** The next cycle the CPU should be scheduled, given a cache
109     * access or quiesce event returning on this cycle.  This function
110     * may return curTick() if the CPU should run on the current cycle.
111     */
112    Tick nextCycle();
113
114    /** The next cycle the CPU should be scheduled, given a cache
115     * access or quiesce event returning on the given Tick.  This
116     * function may return curTick() if the CPU should run on the
117     * current cycle.
118     * @param begin_tick The tick that the event is completing on.
119     */
120    Tick nextCycle(Tick begin_tick);
121
122    TheISA::MicrocodeRom microcodeRom;
123
124#if FULL_SYSTEM
125  protected:
126    TheISA::Interrupts *interrupts;
127
128  public:
129    TheISA::Interrupts *
130    getInterruptController()
131    {
132        return interrupts;
133    }
134
135    virtual void wakeup() = 0;
136
137    void
138    postInterrupt(int int_num, int index)
139    {
140        interrupts->post(int_num, index);
141        wakeup();
142    }
143
144    void
145    clearInterrupt(int int_num, int index)
146    {
147        interrupts->clear(int_num, index);
148    }
149
150    void
151    clearInterrupts()
152    {
153        interrupts->clearAll();
154    }
155
156    bool
157    checkInterrupts(ThreadContext *tc) const
158    {
159        return interrupts->checkInterrupts(tc);
160    }
161
162    class ProfileEvent : public Event
163    {
164      private:
165        BaseCPU *cpu;
166        Tick interval;
167
168      public:
169        ProfileEvent(BaseCPU *cpu, Tick interval);
170        void process();
171    };
172    ProfileEvent *profileEvent;
173#endif
174
175  protected:
176    std::vector<ThreadContext *> threadContexts;
177    std::vector<TheISA::Predecoder *> predecoders;
178
179    Trace::InstTracer * tracer;
180
181  public:
182
183    // Mask to align PCs to MachInst sized boundaries
184    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
185
186    /// Provide access to the tracer pointer
187    Trace::InstTracer * getTracer() { return tracer; }
188
189    /// Notify the CPU that the indicated context is now active.  The
190    /// delay parameter indicates the number of ticks to wait before
191    /// executing (typically 0 or 1).
192    virtual void activateContext(int thread_num, int delay) {}
193
194    /// Notify the CPU that the indicated context is now suspended.
195    virtual void suspendContext(int thread_num) {}
196
197    /// Notify the CPU that the indicated context is now deallocated.
198    virtual void deallocateContext(int thread_num) {}
199
200    /// Notify the CPU that the indicated context is now halted.
201    virtual void haltContext(int thread_num) {}
202
203   /// Given a Thread Context pointer return the thread num
204   int findContext(ThreadContext *tc);
205
206   /// Given a thread num get tho thread context for it
207   ThreadContext *getContext(int tn) { return threadContexts[tn]; }
208
209  public:
210    typedef BaseCPUParams Params;
211    const Params *params() const
212    { return reinterpret_cast<const Params *>(_params); }
213    BaseCPU(Params *params);
214    virtual ~BaseCPU();
215
216    virtual void init();
217    virtual void startup();
218    virtual void regStats();
219
220    virtual void activateWhenReady(ThreadID tid) {};
221
222    void registerThreadContexts();
223
224    /// Prepare for another CPU to take over execution.  When it is
225    /// is ready (drained pipe) it signals the sampler.
226    virtual void switchOut();
227
228    /// Take over execution from the given CPU.  Used for warm-up and
229    /// sampling.
230    virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
231
232    /**
233     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
234     * This is a constant for the duration of the simulation.
235     */
236    ThreadID numThreads;
237
238    TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
239
240    /**
241     * Vector of per-thread instruction-based event queues.  Used for
242     * scheduling events based on number of instructions committed by
243     * a particular thread.
244     */
245    EventQueue **comInstEventQueue;
246
247    /**
248     * Vector of per-thread load-based event queues.  Used for
249     * scheduling events based on number of loads committed by
250     *a particular thread.
251     */
252    EventQueue **comLoadEventQueue;
253
254    System *system;
255
256    Tick phase;
257
258#if FULL_SYSTEM
259    /**
260     * Serialize this object to the given output stream.
261     * @param os The stream to serialize to.
262     */
263    virtual void serialize(std::ostream &os);
264
265    /**
266     * Reconstruct the state of this object from a checkpoint.
267     * @param cp The checkpoint use.
268     * @param section The section name of this object
269     */
270    virtual void unserialize(Checkpoint *cp, const std::string &section);
271
272#endif
273
274    /**
275     * Return pointer to CPU's branch predictor (NULL if none).
276     * @return Branch predictor pointer.
277     */
278    virtual BranchPred *getBranchPred() { return NULL; };
279
280    virtual Counter totalInstructions() const = 0;
281
282    // Function tracing
283  private:
284    bool functionTracingEnabled;
285    std::ostream *functionTraceStream;
286    Addr currentFunctionStart;
287    Addr currentFunctionEnd;
288    Tick functionEntryTick;
289    void enableFunctionTrace();
290    void traceFunctionsInternal(Addr pc);
291
292  protected:
293    void traceFunctions(Addr pc)
294    {
295        if (functionTracingEnabled)
296            traceFunctionsInternal(pc);
297    }
298
299  private:
300    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
301
302  public:
303    static int numSimulatedCPUs() { return cpuList.size(); }
304    static Counter numSimulatedInstructions()
305    {
306        Counter total = 0;
307
308        int size = cpuList.size();
309        for (int i = 0; i < size; ++i)
310            total += cpuList[i]->totalInstructions();
311
312        return total;
313    }
314
315  public:
316    // Number of CPU cycles simulated
317    Stats::Scalar numCycles;
318};
319
320#endif // __CPU_BASE_HH__
321