base.hh revision 6144:e330f7bc22ef
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "arch/microcode_rom.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "sim/eventq.hh"
42#include "sim/insttracer.hh"
43#include "mem/mem_object.hh"
44
45#if FULL_SYSTEM
46#include "arch/interrupts.hh"
47#endif
48
49class BaseCPUParams;
50class BranchPred;
51class CheckerCPU;
52class ThreadContext;
53class System;
54class Port;
55
56namespace TheISA
57{
58    class Predecoder;
59}
60
61class CPUProgressEvent : public Event
62{
63  protected:
64    Tick _interval;
65    Counter lastNumInst;
66    BaseCPU *cpu;
67    bool _repeatEvent;
68
69  public:
70    CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
71
72    void process();
73
74    void interval(Tick ival) { _interval = ival; }
75    Tick interval() { return _interval; }
76
77    void repeatEvent(bool repeat) { _repeatEvent = repeat; }
78
79    virtual const char *description() const;
80};
81
82class BaseCPU : public MemObject
83{
84  protected:
85    // CPU's clock period in terms of the number of ticks of curTime.
86    Tick clock;
87    // @todo remove me after debugging with legion done
88    Tick instCnt;
89    // every cpu has an id, put it in the base cpu
90    // Set at initialization, only time a cpuId might change is during a
91    // takeover (which should be done from within the BaseCPU anyway,
92    // therefore no setCpuId() method is provided
93    int _cpuId;
94
95  public:
96    /** Reads this CPU's ID. */
97    int cpuId() { return _cpuId; }
98
99//    Tick currentTick;
100    inline Tick frequency() const { return Clock::Frequency / clock; }
101    inline Tick ticks(int numCycles) const { return clock * numCycles; }
102    inline Tick curCycle() const { return curTick / clock; }
103    inline Tick tickToCycles(Tick val) const { return val / clock; }
104    // @todo remove me after debugging with legion done
105    Tick instCount() { return instCnt; }
106
107    /** The next cycle the CPU should be scheduled, given a cache
108     * access or quiesce event returning on this cycle.  This function
109     * may return curTick if the CPU should run on the current cycle.
110     */
111    Tick nextCycle();
112
113    /** The next cycle the CPU should be scheduled, given a cache
114     * access or quiesce event returning on the given Tick.  This
115     * function may return curTick if the CPU should run on the
116     * current cycle.
117     * @param begin_tick The tick that the event is completing on.
118     */
119    Tick nextCycle(Tick begin_tick);
120
121    TheISA::MicrocodeRom microcodeRom;
122
123#if FULL_SYSTEM
124  protected:
125    TheISA::Interrupts *interrupts;
126
127  public:
128    TheISA::Interrupts *
129    getInterruptController()
130    {
131        return interrupts;
132    }
133
134    virtual void wakeup() = 0;
135
136    void
137    postInterrupt(int int_num, int index)
138    {
139        interrupts->post(int_num, index);
140        wakeup();
141    }
142
143    void
144    clearInterrupt(int int_num, int index)
145    {
146        interrupts->clear(int_num, index);
147    }
148
149    void
150    clearInterrupts()
151    {
152        interrupts->clearAll();
153    }
154
155    bool
156    checkInterrupts(ThreadContext *tc) const
157    {
158        return interrupts->checkInterrupts(tc);
159    }
160
161    class ProfileEvent : public Event
162    {
163      private:
164        BaseCPU *cpu;
165        Tick interval;
166
167      public:
168        ProfileEvent(BaseCPU *cpu, Tick interval);
169        void process();
170    };
171    ProfileEvent *profileEvent;
172#endif
173
174  protected:
175    std::vector<ThreadContext *> threadContexts;
176    std::vector<TheISA::Predecoder *> predecoders;
177
178    Trace::InstTracer * tracer;
179
180  public:
181
182    /// Provide access to the tracer pointer
183    Trace::InstTracer * getTracer() { return tracer; }
184
185    /// Notify the CPU that the indicated context is now active.  The
186    /// delay parameter indicates the number of ticks to wait before
187    /// executing (typically 0 or 1).
188    virtual void activateContext(int thread_num, int delay) {}
189
190    /// Notify the CPU that the indicated context is now suspended.
191    virtual void suspendContext(int thread_num) {}
192
193    /// Notify the CPU that the indicated context is now deallocated.
194    virtual void deallocateContext(int thread_num) {}
195
196    /// Notify the CPU that the indicated context is now halted.
197    virtual void haltContext(int thread_num) {}
198
199   /// Given a Thread Context pointer return the thread num
200   int findContext(ThreadContext *tc);
201
202   /// Given a thread num get tho thread context for it
203   ThreadContext *getContext(int tn) { return threadContexts[tn]; }
204
205  public:
206    typedef BaseCPUParams Params;
207    const Params *params() const
208    { return reinterpret_cast<const Params *>(_params); }
209    BaseCPU(Params *params);
210    virtual ~BaseCPU();
211
212    virtual void init();
213    virtual void startup();
214    virtual void regStats();
215
216    virtual void activateWhenReady(int tid) {};
217
218    void registerThreadContexts();
219
220    /// Prepare for another CPU to take over execution.  When it is
221    /// is ready (drained pipe) it signals the sampler.
222    virtual void switchOut();
223
224    /// Take over execution from the given CPU.  Used for warm-up and
225    /// sampling.
226    virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
227
228    /**
229     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
230     * This is a constant for the duration of the simulation.
231     */
232    int number_of_threads;
233
234    TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
235
236    /**
237     * Vector of per-thread instruction-based event queues.  Used for
238     * scheduling events based on number of instructions committed by
239     * a particular thread.
240     */
241    EventQueue **comInstEventQueue;
242
243    /**
244     * Vector of per-thread load-based event queues.  Used for
245     * scheduling events based on number of loads committed by
246     *a particular thread.
247     */
248    EventQueue **comLoadEventQueue;
249
250    System *system;
251
252    Tick phase;
253
254#if FULL_SYSTEM
255    /**
256     * Serialize this object to the given output stream.
257     * @param os The stream to serialize to.
258     */
259    virtual void serialize(std::ostream &os);
260
261    /**
262     * Reconstruct the state of this object from a checkpoint.
263     * @param cp The checkpoint use.
264     * @param section The section name of this object
265     */
266    virtual void unserialize(Checkpoint *cp, const std::string &section);
267
268#endif
269
270    /**
271     * Return pointer to CPU's branch predictor (NULL if none).
272     * @return Branch predictor pointer.
273     */
274    virtual BranchPred *getBranchPred() { return NULL; };
275
276    virtual Counter totalInstructions() const { return 0; }
277
278    // Function tracing
279  private:
280    bool functionTracingEnabled;
281    std::ostream *functionTraceStream;
282    Addr currentFunctionStart;
283    Addr currentFunctionEnd;
284    Tick functionEntryTick;
285    void enableFunctionTrace();
286    void traceFunctionsInternal(Addr pc);
287
288  protected:
289    void traceFunctions(Addr pc)
290    {
291        if (functionTracingEnabled)
292            traceFunctionsInternal(pc);
293    }
294
295  private:
296    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
297
298  public:
299    static int numSimulatedCPUs() { return cpuList.size(); }
300    static Counter numSimulatedInstructions()
301    {
302        Counter total = 0;
303
304        int size = cpuList.size();
305        for (int i = 0; i < size; ++i)
306            total += cpuList[i]->totalInstructions();
307
308        return total;
309    }
310
311  public:
312    // Number of CPU cycles simulated
313    Stats::Scalar numCycles;
314};
315
316#endif // __CPU_BASE_HH__
317