base.hh revision 5715:e8c1d4e669a7
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "arch/microcode_rom.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "sim/eventq.hh"
42#include "sim/insttracer.hh"
43#include "mem/mem_object.hh"
44
45#if FULL_SYSTEM
46#include "arch/interrupts.hh"
47#endif
48
49class BaseCPUParams;
50class BranchPred;
51class CheckerCPU;
52class ThreadContext;
53class System;
54class Port;
55
56namespace TheISA
57{
58    class Predecoder;
59}
60
61class CPUProgressEvent : public Event
62{
63  protected:
64    Tick interval;
65    Counter lastNumInst;
66    BaseCPU *cpu;
67
68  public:
69    CPUProgressEvent(BaseCPU *_cpu, Tick ival);
70
71    void process();
72
73    virtual const char *description() const;
74};
75
76class BaseCPU : public MemObject
77{
78  protected:
79    // CPU's clock period in terms of the number of ticks of curTime.
80    Tick clock;
81    // @todo remove me after debugging with legion done
82    Tick instCnt;
83    // every cpu has an id, put it in the base cpu
84    // Set at initialization, only time a cpuId might change is during a
85    // takeover (which should be done from within the BaseCPU anyway,
86    // therefore no setCpuId() method is provided
87    int _cpuId;
88
89  public:
90    /** Reads this CPU's ID. */
91    int cpuId() { return _cpuId; }
92
93//    Tick currentTick;
94    inline Tick frequency() const { return Clock::Frequency / clock; }
95    inline Tick ticks(int numCycles) const { return clock * numCycles; }
96    inline Tick curCycle() const { return curTick / clock; }
97    inline Tick tickToCycles(Tick val) const { return val / clock; }
98    // @todo remove me after debugging with legion done
99    Tick instCount() { return instCnt; }
100
101    /** The next cycle the CPU should be scheduled, given a cache
102     * access or quiesce event returning on this cycle.  This function
103     * may return curTick if the CPU should run on the current cycle.
104     */
105    Tick nextCycle();
106
107    /** The next cycle the CPU should be scheduled, given a cache
108     * access or quiesce event returning on the given Tick.  This
109     * function may return curTick if the CPU should run on the
110     * current cycle.
111     * @param begin_tick The tick that the event is completing on.
112     */
113    Tick nextCycle(Tick begin_tick);
114
115    TheISA::MicrocodeRom microcodeRom;
116
117#if FULL_SYSTEM
118  protected:
119    TheISA::Interrupts *interrupts;
120
121  public:
122    TheISA::Interrupts *
123    getInterruptController()
124    {
125        return interrupts;
126    }
127
128    virtual void postInterrupt(int int_num, int index);
129    virtual void clearInterrupt(int int_num, int index);
130    virtual void clearInterrupts();
131
132    bool
133    checkInterrupts(ThreadContext *tc) const
134    {
135        return interrupts->checkInterrupts(tc);
136    }
137
138    class ProfileEvent : public Event
139    {
140      private:
141        BaseCPU *cpu;
142        Tick interval;
143
144      public:
145        ProfileEvent(BaseCPU *cpu, Tick interval);
146        void process();
147    };
148    ProfileEvent *profileEvent;
149#endif
150
151  protected:
152    std::vector<ThreadContext *> threadContexts;
153    std::vector<TheISA::Predecoder *> predecoders;
154
155    Trace::InstTracer * tracer;
156
157  public:
158
159    /// Provide access to the tracer pointer
160    Trace::InstTracer * getTracer() { return tracer; }
161
162    /// Notify the CPU that the indicated context is now active.  The
163    /// delay parameter indicates the number of ticks to wait before
164    /// executing (typically 0 or 1).
165    virtual void activateContext(int thread_num, int delay) {}
166
167    /// Notify the CPU that the indicated context is now suspended.
168    virtual void suspendContext(int thread_num) {}
169
170    /// Notify the CPU that the indicated context is now deallocated.
171    virtual void deallocateContext(int thread_num) {}
172
173    /// Notify the CPU that the indicated context is now halted.
174    virtual void haltContext(int thread_num) {}
175
176   /// Given a Thread Context pointer return the thread num
177   int findContext(ThreadContext *tc);
178
179   /// Given a thread num get tho thread context for it
180   ThreadContext *getContext(int tn) { return threadContexts[tn]; }
181
182  public:
183    typedef BaseCPUParams Params;
184    const Params *params() const
185    { return reinterpret_cast<const Params *>(_params); }
186    BaseCPU(Params *params);
187    virtual ~BaseCPU();
188
189    virtual void init();
190    virtual void startup();
191    virtual void regStats();
192
193    virtual void activateWhenReady(int tid) {};
194
195    void registerThreadContexts();
196
197    /// Prepare for another CPU to take over execution.  When it is
198    /// is ready (drained pipe) it signals the sampler.
199    virtual void switchOut();
200
201    /// Take over execution from the given CPU.  Used for warm-up and
202    /// sampling.
203    virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
204
205    /**
206     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
207     * This is a constant for the duration of the simulation.
208     */
209    int number_of_threads;
210
211    TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
212
213    /**
214     * Vector of per-thread instruction-based event queues.  Used for
215     * scheduling events based on number of instructions committed by
216     * a particular thread.
217     */
218    EventQueue **comInstEventQueue;
219
220    /**
221     * Vector of per-thread load-based event queues.  Used for
222     * scheduling events based on number of loads committed by
223     *a particular thread.
224     */
225    EventQueue **comLoadEventQueue;
226
227    System *system;
228
229    Tick phase;
230
231#if FULL_SYSTEM
232    /**
233     * Serialize this object to the given output stream.
234     * @param os The stream to serialize to.
235     */
236    virtual void serialize(std::ostream &os);
237
238    /**
239     * Reconstruct the state of this object from a checkpoint.
240     * @param cp The checkpoint use.
241     * @param section The section name of this object
242     */
243    virtual void unserialize(Checkpoint *cp, const std::string &section);
244
245#endif
246
247    /**
248     * Return pointer to CPU's branch predictor (NULL if none).
249     * @return Branch predictor pointer.
250     */
251    virtual BranchPred *getBranchPred() { return NULL; };
252
253    virtual Counter totalInstructions() const { return 0; }
254
255    // Function tracing
256  private:
257    bool functionTracingEnabled;
258    std::ostream *functionTraceStream;
259    Addr currentFunctionStart;
260    Addr currentFunctionEnd;
261    Tick functionEntryTick;
262    void enableFunctionTrace();
263    void traceFunctionsInternal(Addr pc);
264
265  protected:
266    void traceFunctions(Addr pc)
267    {
268        if (functionTracingEnabled)
269            traceFunctionsInternal(pc);
270    }
271
272  private:
273    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
274
275  public:
276    static int numSimulatedCPUs() { return cpuList.size(); }
277    static Counter numSimulatedInstructions()
278    {
279        Counter total = 0;
280
281        int size = cpuList.size();
282        for (int i = 0; i < size; ++i)
283            total += cpuList[i]->totalInstructions();
284
285        return total;
286    }
287
288  public:
289    // Number of CPU cycles simulated
290    Stats::Scalar<> numCycles;
291};
292
293#endif // __CPU_BASE_HH__
294