base.hh revision 5704:98224505352a
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "arch/isa_traits.hh" 38#include "arch/microcode_rom.hh" 39#include "base/statistics.hh" 40#include "config/full_system.hh" 41#include "sim/eventq.hh" 42#include "sim/insttracer.hh" 43#include "mem/mem_object.hh" 44 45#if FULL_SYSTEM 46#include "arch/interrupts.hh" 47#endif 48 49class BaseCPUParams; 50class BranchPred; 51class CheckerCPU; 52class ThreadContext; 53class System; 54class Port; 55 56namespace TheISA 57{ 58 class Predecoder; 59} 60 61class CPUProgressEvent : public Event 62{ 63 protected: 64 Tick interval; 65 Counter lastNumInst; 66 BaseCPU *cpu; 67 68 public: 69 CPUProgressEvent(BaseCPU *_cpu, Tick ival); 70 71 void process(); 72 73 virtual const char *description() const; 74}; 75 76class BaseCPU : public MemObject 77{ 78 protected: 79 // CPU's clock period in terms of the number of ticks of curTime. 80 Tick clock; 81 // @todo remove me after debugging with legion done 82 Tick instCnt; 83 84 public: 85// Tick currentTick; 86 inline Tick frequency() const { return Clock::Frequency / clock; } 87 inline Tick ticks(int numCycles) const { return clock * numCycles; } 88 inline Tick curCycle() const { return curTick / clock; } 89 inline Tick tickToCycles(Tick val) const { return val / clock; } 90 // @todo remove me after debugging with legion done 91 Tick instCount() { return instCnt; } 92 93 /** The next cycle the CPU should be scheduled, given a cache 94 * access or quiesce event returning on this cycle. This function 95 * may return curTick if the CPU should run on the current cycle. 96 */ 97 Tick nextCycle(); 98 99 /** The next cycle the CPU should be scheduled, given a cache 100 * access or quiesce event returning on the given Tick. This 101 * function may return curTick if the CPU should run on the 102 * current cycle. 103 * @param begin_tick The tick that the event is completing on. 104 */ 105 Tick nextCycle(Tick begin_tick); 106 107 TheISA::MicrocodeRom microcodeRom; 108 109#if FULL_SYSTEM 110 protected: 111 TheISA::Interrupts *interrupts; 112 113 public: 114 TheISA::Interrupts * 115 getInterruptController() 116 { 117 return interrupts; 118 } 119 120 virtual void postInterrupt(int int_num, int index); 121 virtual void clearInterrupt(int int_num, int index); 122 virtual void clearInterrupts(); 123 124 bool 125 checkInterrupts(ThreadContext *tc) const 126 { 127 return interrupts->checkInterrupts(tc); 128 } 129 130 class ProfileEvent : public Event 131 { 132 private: 133 BaseCPU *cpu; 134 Tick interval; 135 136 public: 137 ProfileEvent(BaseCPU *cpu, Tick interval); 138 void process(); 139 }; 140 ProfileEvent *profileEvent; 141#endif 142 143 protected: 144 std::vector<ThreadContext *> threadContexts; 145 std::vector<TheISA::Predecoder *> predecoders; 146 147 Trace::InstTracer * tracer; 148 149 public: 150 151 /// Provide access to the tracer pointer 152 Trace::InstTracer * getTracer() { return tracer; } 153 154 /// Notify the CPU that the indicated context is now active. The 155 /// delay parameter indicates the number of ticks to wait before 156 /// executing (typically 0 or 1). 157 virtual void activateContext(int thread_num, int delay) {} 158 159 /// Notify the CPU that the indicated context is now suspended. 160 virtual void suspendContext(int thread_num) {} 161 162 /// Notify the CPU that the indicated context is now deallocated. 163 virtual void deallocateContext(int thread_num) {} 164 165 /// Notify the CPU that the indicated context is now halted. 166 virtual void haltContext(int thread_num) {} 167 168 /// Given a Thread Context pointer return the thread num 169 int findContext(ThreadContext *tc); 170 171 /// Given a thread num get tho thread context for it 172 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 173 174 public: 175 typedef BaseCPUParams Params; 176 const Params *params() const 177 { return reinterpret_cast<const Params *>(_params); } 178 BaseCPU(Params *params); 179 virtual ~BaseCPU(); 180 181 virtual void init(); 182 virtual void startup(); 183 virtual void regStats(); 184 185 virtual void activateWhenReady(int tid) {}; 186 187 void registerThreadContexts(); 188 189 /// Prepare for another CPU to take over execution. When it is 190 /// is ready (drained pipe) it signals the sampler. 191 virtual void switchOut(); 192 193 /// Take over execution from the given CPU. Used for warm-up and 194 /// sampling. 195 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 196 197 /** 198 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 199 * This is a constant for the duration of the simulation. 200 */ 201 int number_of_threads; 202 203 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 204 205 /** 206 * Vector of per-thread instruction-based event queues. Used for 207 * scheduling events based on number of instructions committed by 208 * a particular thread. 209 */ 210 EventQueue **comInstEventQueue; 211 212 /** 213 * Vector of per-thread load-based event queues. Used for 214 * scheduling events based on number of loads committed by 215 *a particular thread. 216 */ 217 EventQueue **comLoadEventQueue; 218 219 System *system; 220 221 Tick phase; 222 223#if FULL_SYSTEM 224 /** 225 * Serialize this object to the given output stream. 226 * @param os The stream to serialize to. 227 */ 228 virtual void serialize(std::ostream &os); 229 230 /** 231 * Reconstruct the state of this object from a checkpoint. 232 * @param cp The checkpoint use. 233 * @param section The section name of this object 234 */ 235 virtual void unserialize(Checkpoint *cp, const std::string §ion); 236 237#endif 238 239 /** 240 * Return pointer to CPU's branch predictor (NULL if none). 241 * @return Branch predictor pointer. 242 */ 243 virtual BranchPred *getBranchPred() { return NULL; }; 244 245 virtual Counter totalInstructions() const { return 0; } 246 247 // Function tracing 248 private: 249 bool functionTracingEnabled; 250 std::ostream *functionTraceStream; 251 Addr currentFunctionStart; 252 Addr currentFunctionEnd; 253 Tick functionEntryTick; 254 void enableFunctionTrace(); 255 void traceFunctionsInternal(Addr pc); 256 257 protected: 258 void traceFunctions(Addr pc) 259 { 260 if (functionTracingEnabled) 261 traceFunctionsInternal(pc); 262 } 263 264 private: 265 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 266 267 public: 268 static int numSimulatedCPUs() { return cpuList.size(); } 269 static Counter numSimulatedInstructions() 270 { 271 Counter total = 0; 272 273 int size = cpuList.size(); 274 for (int i = 0; i < size; ++i) 275 total += cpuList[i]->totalInstructions(); 276 277 return total; 278 } 279 280 public: 281 // Number of CPU cycles simulated 282 Stats::Scalar<> numCycles; 283}; 284 285#endif // __CPU_BASE_HH__ 286