base.hh revision 3814:33bd4ec9d66a
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_BASE_HH__ 33#define __CPU_BASE_HH__ 34 35#include <vector> 36 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "sim/eventq.hh" 40#include "mem/mem_object.hh" 41#include "arch/isa_traits.hh" 42 43#if FULL_SYSTEM 44#include "arch/interrupts.hh" 45#endif 46 47class BranchPred; 48class CheckerCPU; 49class ThreadContext; 50class System; 51class Port; 52 53class CPUProgressEvent : public Event 54{ 55 protected: 56 Tick interval; 57 Counter lastNumInst; 58 BaseCPU *cpu; 59 60 public: 61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 62 63 void process(); 64 65 virtual const char *description(); 66}; 67 68class BaseCPU : public MemObject 69{ 70 protected: 71 // CPU's clock period in terms of the number of ticks of curTime. 72 Tick clock; 73 // @todo remove me after debugging with legion done 74 Tick instCnt; 75 76 public: 77// Tick currentTick; 78 inline Tick frequency() const { return Clock::Frequency / clock; } 79 inline Tick cycles(int numCycles) const { return clock * numCycles; } 80 inline Tick curCycle() const { return curTick / clock; } 81 // @todo remove me after debugging with legion done 82 Tick instCount() { return instCnt; } 83 84 /** The next cycle the CPU should be scheduled, given a cache 85 * access or quiesce event returning on this cycle. This function 86 * may return curTick if the CPU should run on the current cycle. 87 */ 88 Tick nextCycle(); 89 90 /** The next cycle the CPU should be scheduled, given a cache 91 * access or quiesce event returning on the given Tick. This 92 * function may return curTick if the CPU should run on the 93 * current cycle. 94 * @param begin_tick The tick that the event is completing on. 95 */ 96 Tick nextCycle(Tick begin_tick); 97 98#if FULL_SYSTEM 99 protected: 100// uint64_t interrupts[TheISA::NumInterruptLevels]; 101// uint64_t intstatus; 102 TheISA::Interrupts interrupts; 103 104 public: 105 virtual void post_interrupt(int int_num, int index); 106 virtual void clear_interrupt(int int_num, int index); 107 virtual void clear_interrupts(); 108 bool checkInterrupts; 109 110 bool check_interrupts(ThreadContext * tc) const 111 { return interrupts.check_interrupts(tc); } 112 113 class ProfileEvent : public Event 114 { 115 private: 116 BaseCPU *cpu; 117 int interval; 118 119 public: 120 ProfileEvent(BaseCPU *cpu, int interval); 121 void process(); 122 }; 123 ProfileEvent *profileEvent; 124#endif 125 126 protected: 127 std::vector<ThreadContext *> threadContexts; 128 129 public: 130 131 /// Notify the CPU that the indicated context is now active. The 132 /// delay parameter indicates the number of ticks to wait before 133 /// executing (typically 0 or 1). 134 virtual void activateContext(int thread_num, int delay) {} 135 136 /// Notify the CPU that the indicated context is now suspended. 137 virtual void suspendContext(int thread_num) {} 138 139 /// Notify the CPU that the indicated context is now deallocated. 140 virtual void deallocateContext(int thread_num) {} 141 142 /// Notify the CPU that the indicated context is now halted. 143 virtual void haltContext(int thread_num) {} 144 145 public: 146 struct Params 147 { 148 std::string name; 149 int numberOfThreads; 150 bool deferRegistration; 151 Counter max_insts_any_thread; 152 Counter max_insts_all_threads; 153 Counter max_loads_any_thread; 154 Counter max_loads_all_threads; 155 Tick clock; 156 bool functionTrace; 157 Tick functionTraceStart; 158 System *system; 159 int cpu_id; 160 Tick phase; 161#if FULL_SYSTEM 162 Tick profile; 163 164 bool do_statistics_insts; 165 bool do_checkpoint_insts; 166 bool do_quiesce; 167#endif 168 Tick progress_interval; 169 BaseCPU *checker; 170 171 Params(); 172 }; 173 174 const Params *params; 175 176 BaseCPU(Params *params); 177 virtual ~BaseCPU(); 178 179 virtual void init(); 180 virtual void startup(); 181 virtual void regStats(); 182 183 virtual void activateWhenReady(int tid) {}; 184 185 void registerThreadContexts(); 186 187 /// Prepare for another CPU to take over execution. When it is 188 /// is ready (drained pipe) it signals the sampler. 189 virtual void switchOut(); 190 191 /// Take over execution from the given CPU. Used for warm-up and 192 /// sampling. 193 virtual void takeOverFrom(BaseCPU *); 194 195 /** 196 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 197 * This is a constant for the duration of the simulation. 198 */ 199 int number_of_threads; 200 201 /** 202 * Vector of per-thread instruction-based event queues. Used for 203 * scheduling events based on number of instructions committed by 204 * a particular thread. 205 */ 206 EventQueue **comInstEventQueue; 207 208 /** 209 * Vector of per-thread load-based event queues. Used for 210 * scheduling events based on number of loads committed by 211 *a particular thread. 212 */ 213 EventQueue **comLoadEventQueue; 214 215 System *system; 216 217 Tick phase; 218 219#if FULL_SYSTEM 220 /** 221 * Serialize this object to the given output stream. 222 * @param os The stream to serialize to. 223 */ 224 virtual void serialize(std::ostream &os); 225 226 /** 227 * Reconstruct the state of this object from a checkpoint. 228 * @param cp The checkpoint use. 229 * @param section The section name of this object 230 */ 231 virtual void unserialize(Checkpoint *cp, const std::string §ion); 232 233#endif 234 235 /** 236 * Return pointer to CPU's branch predictor (NULL if none). 237 * @return Branch predictor pointer. 238 */ 239 virtual BranchPred *getBranchPred() { return NULL; }; 240 241 virtual Counter totalInstructions() const { return 0; } 242 243 // Function tracing 244 private: 245 bool functionTracingEnabled; 246 std::ostream *functionTraceStream; 247 Addr currentFunctionStart; 248 Addr currentFunctionEnd; 249 Tick functionEntryTick; 250 void enableFunctionTrace(); 251 void traceFunctionsInternal(Addr pc); 252 253 protected: 254 void traceFunctions(Addr pc) 255 { 256 if (functionTracingEnabled) 257 traceFunctionsInternal(pc); 258 } 259 260 private: 261 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 262 263 public: 264 static int numSimulatedCPUs() { return cpuList.size(); } 265 static Counter numSimulatedInstructions() 266 { 267 Counter total = 0; 268 269 int size = cpuList.size(); 270 for (int i = 0; i < size; ++i) 271 total += cpuList[i]->totalInstructions(); 272 273 return total; 274 } 275 276 public: 277 // Number of CPU cycles simulated 278 Stats::Scalar<> numCycles; 279}; 280 281#endif // __CPU_BASE_HH__ 282