base.hh revision 3521:0b0b3551def0 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43#if FULL_SYSTEM
44#include "arch/interrupts.hh"
45#endif
46
47class BranchPred;
48class CheckerCPU;
49class ThreadContext;
50class System;
51class Port;
52
53class CPUProgressEvent : public Event
54{
55  protected:
56    Tick interval;
57    Counter lastNumInst;
58    BaseCPU *cpu;
59
60  public:
61    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
62
63    void process();
64
65    virtual const char *description();
66};
67
68class BaseCPU : public MemObject
69{
70  protected:
71    // CPU's clock period in terms of the number of ticks of curTime.
72    Tick clock;
73
74  public:
75//    Tick currentTick;
76    inline Tick frequency() const { return Clock::Frequency / clock; }
77    inline Tick cycles(int numCycles) const { return clock * numCycles; }
78    inline Tick curCycle() const { return curTick / clock; }
79
80#if FULL_SYSTEM
81  protected:
82//    uint64_t interrupts[TheISA::NumInterruptLevels];
83//    uint64_t intstatus;
84    TheISA::Interrupts interrupts;
85
86  public:
87    virtual void post_interrupt(int int_num, int index);
88    virtual void clear_interrupt(int int_num, int index);
89    virtual void clear_interrupts();
90    bool checkInterrupts;
91
92    bool check_interrupts(ThreadContext * tc) const
93    { return interrupts.check_interrupts(tc); }
94
95    class ProfileEvent : public Event
96    {
97      private:
98        BaseCPU *cpu;
99        int interval;
100
101      public:
102        ProfileEvent(BaseCPU *cpu, int interval);
103        void process();
104    };
105    ProfileEvent *profileEvent;
106#endif
107
108  protected:
109    std::vector<ThreadContext *> threadContexts;
110
111  public:
112
113    /// Notify the CPU that the indicated context is now active.  The
114    /// delay parameter indicates the number of ticks to wait before
115    /// executing (typically 0 or 1).
116    virtual void activateContext(int thread_num, int delay) {}
117
118    /// Notify the CPU that the indicated context is now suspended.
119    virtual void suspendContext(int thread_num) {}
120
121    /// Notify the CPU that the indicated context is now deallocated.
122    virtual void deallocateContext(int thread_num) {}
123
124    /// Notify the CPU that the indicated context is now halted.
125    virtual void haltContext(int thread_num) {}
126
127  public:
128    struct Params
129    {
130        std::string name;
131        int numberOfThreads;
132        bool deferRegistration;
133        Counter max_insts_any_thread;
134        Counter max_insts_all_threads;
135        Counter max_loads_any_thread;
136        Counter max_loads_all_threads;
137        Tick clock;
138        bool functionTrace;
139        Tick functionTraceStart;
140        System *system;
141        int cpu_id;
142#if FULL_SYSTEM
143        Tick profile;
144#endif
145        Tick progress_interval;
146        BaseCPU *checker;
147
148        Params();
149    };
150
151    const Params *params;
152
153    BaseCPU(Params *params);
154    virtual ~BaseCPU();
155
156    virtual void init();
157    virtual void startup();
158    virtual void regStats();
159
160    virtual void activateWhenReady(int tid) {};
161
162    void registerThreadContexts();
163
164    /// Prepare for another CPU to take over execution.  When it is
165    /// is ready (drained pipe) it signals the sampler.
166    virtual void switchOut();
167
168    /// Take over execution from the given CPU.  Used for warm-up and
169    /// sampling.
170    virtual void takeOverFrom(BaseCPU *);
171
172    /**
173     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
174     * This is a constant for the duration of the simulation.
175     */
176    int number_of_threads;
177
178    /**
179     * Vector of per-thread instruction-based event queues.  Used for
180     * scheduling events based on number of instructions committed by
181     * a particular thread.
182     */
183    EventQueue **comInstEventQueue;
184
185    /**
186     * Vector of per-thread load-based event queues.  Used for
187     * scheduling events based on number of loads committed by
188     *a particular thread.
189     */
190    EventQueue **comLoadEventQueue;
191
192    System *system;
193
194#if FULL_SYSTEM
195    /**
196     * Serialize this object to the given output stream.
197     * @param os The stream to serialize to.
198     */
199    virtual void serialize(std::ostream &os);
200
201    /**
202     * Reconstruct the state of this object from a checkpoint.
203     * @param cp The checkpoint use.
204     * @param section The section name of this object
205     */
206    virtual void unserialize(Checkpoint *cp, const std::string &section);
207
208#endif
209
210    /**
211     * Return pointer to CPU's branch predictor (NULL if none).
212     * @return Branch predictor pointer.
213     */
214    virtual BranchPred *getBranchPred() { return NULL; };
215
216    virtual Counter totalInstructions() const { return 0; }
217
218    // Function tracing
219  private:
220    bool functionTracingEnabled;
221    std::ostream *functionTraceStream;
222    Addr currentFunctionStart;
223    Addr currentFunctionEnd;
224    Tick functionEntryTick;
225    void enableFunctionTrace();
226    void traceFunctionsInternal(Addr pc);
227
228  protected:
229    void traceFunctions(Addr pc)
230    {
231        if (functionTracingEnabled)
232            traceFunctionsInternal(pc);
233    }
234
235  private:
236    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
237
238  public:
239    static int numSimulatedCPUs() { return cpuList.size(); }
240    static Counter numSimulatedInstructions()
241    {
242        Counter total = 0;
243
244        int size = cpuList.size();
245        for (int i = 0; i < size; ++i)
246            total += cpuList[i]->totalInstructions();
247
248        return total;
249    }
250
251  public:
252    // Number of CPU cycles simulated
253    Stats::Scalar<> numCycles;
254};
255
256#endif // __CPU_BASE_HH__
257