base.hh revision 3520 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43#if FULL_SYSTEM
44#include "arch/interrupts.hh"
45#endif
46
47class BranchPred;
48class CheckerCPU;
49class ThreadContext;
50class System;
51class Port;
52
53class CPUProgressEvent : public Event
54{
55  protected:
56    Tick interval;
57    Counter lastNumInst;
58    BaseCPU *cpu;
59
60  public:
61    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
62
63    void process();
64
65    virtual const char *description();
66};
67
68class BaseCPU : public MemObject
69{
70  protected:
71    // CPU's clock period in terms of the number of ticks of curTime.
72    Tick clock;
73
74  public:
75//    Tick currentTick;
76    inline Tick frequency() const { return Clock::Frequency / clock; }
77    inline Tick cycles(int numCycles) const { return clock * numCycles; }
78    inline Tick curCycle() const { return curTick / clock; }
79
80#if FULL_SYSTEM
81  protected:
82//    uint64_t interrupts[TheISA::NumInterruptLevels];
83//    uint64_t intstatus;
84    TheISA::Interrupts interrupts;
85
86  public:
87    virtual void post_interrupt(int int_num, int index);
88    virtual void clear_interrupt(int int_num, int index);
89    virtual void clear_interrupts();
90    bool checkInterrupts;
91
92    bool check_interrupt(int int_num) const {
93        return interrupts.check_interrupt(int_num);
94    }
95
96    bool check_interrupts() const { return interrupts.check_interrupts(); }
97    //uint64_t intr_status() const { return interrupts.intr_status(); }
98
99    class ProfileEvent : public Event
100    {
101      private:
102        BaseCPU *cpu;
103        int interval;
104
105      public:
106        ProfileEvent(BaseCPU *cpu, int interval);
107        void process();
108    };
109    ProfileEvent *profileEvent;
110#endif
111
112  protected:
113    std::vector<ThreadContext *> threadContexts;
114
115  public:
116
117    /// Notify the CPU that the indicated context is now active.  The
118    /// delay parameter indicates the number of ticks to wait before
119    /// executing (typically 0 or 1).
120    virtual void activateContext(int thread_num, int delay) {}
121
122    /// Notify the CPU that the indicated context is now suspended.
123    virtual void suspendContext(int thread_num) {}
124
125    /// Notify the CPU that the indicated context is now deallocated.
126    virtual void deallocateContext(int thread_num) {}
127
128    /// Notify the CPU that the indicated context is now halted.
129    virtual void haltContext(int thread_num) {}
130
131  public:
132    struct Params
133    {
134        std::string name;
135        int numberOfThreads;
136        bool deferRegistration;
137        Counter max_insts_any_thread;
138        Counter max_insts_all_threads;
139        Counter max_loads_any_thread;
140        Counter max_loads_all_threads;
141        Tick clock;
142        bool functionTrace;
143        Tick functionTraceStart;
144        System *system;
145        int cpu_id;
146#if FULL_SYSTEM
147        Tick profile;
148#endif
149        Tick progress_interval;
150        BaseCPU *checker;
151
152        Params();
153    };
154
155    const Params *params;
156
157    BaseCPU(Params *params);
158    virtual ~BaseCPU();
159
160    virtual void init();
161    virtual void startup();
162    virtual void regStats();
163
164    virtual void activateWhenReady(int tid) {};
165
166    void registerThreadContexts();
167
168    /// Prepare for another CPU to take over execution.  When it is
169    /// is ready (drained pipe) it signals the sampler.
170    virtual void switchOut();
171
172    /// Take over execution from the given CPU.  Used for warm-up and
173    /// sampling.
174    virtual void takeOverFrom(BaseCPU *);
175
176    /**
177     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
178     * This is a constant for the duration of the simulation.
179     */
180    int number_of_threads;
181
182    /**
183     * Vector of per-thread instruction-based event queues.  Used for
184     * scheduling events based on number of instructions committed by
185     * a particular thread.
186     */
187    EventQueue **comInstEventQueue;
188
189    /**
190     * Vector of per-thread load-based event queues.  Used for
191     * scheduling events based on number of loads committed by
192     *a particular thread.
193     */
194    EventQueue **comLoadEventQueue;
195
196    System *system;
197
198#if FULL_SYSTEM
199    /**
200     * Serialize this object to the given output stream.
201     * @param os The stream to serialize to.
202     */
203    virtual void serialize(std::ostream &os);
204
205    /**
206     * Reconstruct the state of this object from a checkpoint.
207     * @param cp The checkpoint use.
208     * @param section The section name of this object
209     */
210    virtual void unserialize(Checkpoint *cp, const std::string &section);
211
212#endif
213
214    /**
215     * Return pointer to CPU's branch predictor (NULL if none).
216     * @return Branch predictor pointer.
217     */
218    virtual BranchPred *getBranchPred() { return NULL; };
219
220    virtual Counter totalInstructions() const { return 0; }
221
222    // Function tracing
223  private:
224    bool functionTracingEnabled;
225    std::ostream *functionTraceStream;
226    Addr currentFunctionStart;
227    Addr currentFunctionEnd;
228    Tick functionEntryTick;
229    void enableFunctionTrace();
230    void traceFunctionsInternal(Addr pc);
231
232  protected:
233    void traceFunctions(Addr pc)
234    {
235        if (functionTracingEnabled)
236            traceFunctionsInternal(pc);
237    }
238
239  private:
240    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
241
242  public:
243    static int numSimulatedCPUs() { return cpuList.size(); }
244    static Counter numSimulatedInstructions()
245    {
246        Counter total = 0;
247
248        int size = cpuList.size();
249        for (int i = 0; i < size; ++i)
250            total += cpuList[i]->totalInstructions();
251
252        return total;
253    }
254
255  public:
256    // Number of CPU cycles simulated
257    Stats::Scalar<> numCycles;
258};
259
260#endif // __CPU_BASE_HH__
261