base.hh revision 3170:37fd1e73f836 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "sim/eventq.hh"
40#include "mem/mem_object.hh"
41#include "arch/isa_traits.hh"
42
43class BranchPred;
44class CheckerCPU;
45class ThreadContext;
46class System;
47class Port;
48
49class CPUProgressEvent : public Event
50{
51  protected:
52    Tick interval;
53    Counter lastNumInst;
54    BaseCPU *cpu;
55
56  public:
57    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
58
59    void process();
60
61    virtual const char *description();
62};
63
64class BaseCPU : public MemObject
65{
66  protected:
67    // CPU's clock period in terms of the number of ticks of curTime.
68    Tick clock;
69
70  public:
71//    Tick currentTick;
72    inline Tick frequency() const { return Clock::Frequency / clock; }
73    inline Tick cycles(int numCycles) const { return clock * numCycles; }
74    inline Tick curCycle() const { return curTick / clock; }
75
76#if FULL_SYSTEM
77  protected:
78    uint64_t interrupts[TheISA::NumInterruptLevels];
79    uint64_t intstatus;
80
81  public:
82    virtual void post_interrupt(int int_num, int index);
83    virtual void clear_interrupt(int int_num, int index);
84    virtual void clear_interrupts();
85    bool checkInterrupts;
86
87    bool check_interrupt(int int_num) const {
88        if (int_num > TheISA::NumInterruptLevels)
89            panic("int_num out of bounds\n");
90
91        return interrupts[int_num] != 0;
92    }
93
94    bool check_interrupts() const { return intstatus != 0; }
95    uint64_t intr_status() const { return intstatus; }
96
97    class ProfileEvent : public Event
98    {
99      private:
100        BaseCPU *cpu;
101        int interval;
102
103      public:
104        ProfileEvent(BaseCPU *cpu, int interval);
105        void process();
106    };
107    ProfileEvent *profileEvent;
108#endif
109
110  protected:
111    std::vector<ThreadContext *> threadContexts;
112
113  public:
114
115    /// Notify the CPU that the indicated context is now active.  The
116    /// delay parameter indicates the number of ticks to wait before
117    /// executing (typically 0 or 1).
118    virtual void activateContext(int thread_num, int delay) {}
119
120    /// Notify the CPU that the indicated context is now suspended.
121    virtual void suspendContext(int thread_num) {}
122
123    /// Notify the CPU that the indicated context is now deallocated.
124    virtual void deallocateContext(int thread_num) {}
125
126    /// Notify the CPU that the indicated context is now halted.
127    virtual void haltContext(int thread_num) {}
128
129  public:
130    struct Params
131    {
132        std::string name;
133        int numberOfThreads;
134        bool deferRegistration;
135        Counter max_insts_any_thread;
136        Counter max_insts_all_threads;
137        Counter max_loads_any_thread;
138        Counter max_loads_all_threads;
139        Tick clock;
140        bool functionTrace;
141        Tick functionTraceStart;
142        System *system;
143        int cpu_id;
144#if FULL_SYSTEM
145        Tick profile;
146#endif
147        Tick progress_interval;
148        BaseCPU *checker;
149
150        Params();
151    };
152
153    const Params *params;
154
155    BaseCPU(Params *params);
156    virtual ~BaseCPU();
157
158    virtual void init();
159    virtual void startup();
160    virtual void regStats();
161
162    virtual void activateWhenReady(int tid) {};
163
164    void registerThreadContexts();
165
166    /// Prepare for another CPU to take over execution.  When it is
167    /// is ready (drained pipe) it signals the sampler.
168    virtual void switchOut();
169
170    /// Take over execution from the given CPU.  Used for warm-up and
171    /// sampling.
172    virtual void takeOverFrom(BaseCPU *);
173
174    /**
175     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
176     * This is a constant for the duration of the simulation.
177     */
178    int number_of_threads;
179
180    /**
181     * Vector of per-thread instruction-based event queues.  Used for
182     * scheduling events based on number of instructions committed by
183     * a particular thread.
184     */
185    EventQueue **comInstEventQueue;
186
187    /**
188     * Vector of per-thread load-based event queues.  Used for
189     * scheduling events based on number of loads committed by
190     *a particular thread.
191     */
192    EventQueue **comLoadEventQueue;
193
194    System *system;
195
196#if FULL_SYSTEM
197    /**
198     * Serialize this object to the given output stream.
199     * @param os The stream to serialize to.
200     */
201    virtual void serialize(std::ostream &os);
202
203    /**
204     * Reconstruct the state of this object from a checkpoint.
205     * @param cp The checkpoint use.
206     * @param section The section name of this object
207     */
208    virtual void unserialize(Checkpoint *cp, const std::string &section);
209
210#endif
211
212    /**
213     * Return pointer to CPU's branch predictor (NULL if none).
214     * @return Branch predictor pointer.
215     */
216    virtual BranchPred *getBranchPred() { return NULL; };
217
218    virtual Counter totalInstructions() const { return 0; }
219
220    // Function tracing
221  private:
222    bool functionTracingEnabled;
223    std::ostream *functionTraceStream;
224    Addr currentFunctionStart;
225    Addr currentFunctionEnd;
226    Tick functionEntryTick;
227    void enableFunctionTrace();
228    void traceFunctionsInternal(Addr pc);
229
230  protected:
231    void traceFunctions(Addr pc)
232    {
233        if (functionTracingEnabled)
234            traceFunctionsInternal(pc);
235    }
236
237  private:
238    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
239
240  public:
241    static int numSimulatedCPUs() { return cpuList.size(); }
242    static Counter numSimulatedInstructions()
243    {
244        Counter total = 0;
245
246        int size = cpuList.size();
247        for (int i = 0; i < size; ++i)
248            total += cpuList[i]->totalInstructions();
249
250        return total;
251    }
252
253  public:
254    // Number of CPU cycles simulated
255    Stats::Scalar<> numCycles;
256};
257
258#endif // __CPU_BASE_HH__
259