base.hh revision 10529:05b5a6cf3521
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#ifndef __CPU_BASE_HH__ 47#define __CPU_BASE_HH__ 48 49#include <vector> 50 51// Before we do anything else, check if this build is the NULL ISA, 52// and if so stop here 53#include "config/the_isa.hh" 54#if THE_ISA == NULL_ISA 55#include "arch/null/cpu_dummy.hh" 56#else 57#include "arch/interrupts.hh" 58#include "arch/isa_traits.hh" 59#include "arch/microcode_rom.hh" 60#include "base/statistics.hh" 61#include "mem/mem_object.hh" 62#include "sim/eventq.hh" 63#include "sim/full_system.hh" 64#include "sim/insttracer.hh" 65#include "sim/probe/pmu.hh" 66#include "sim/system.hh" 67#include "debug/Mwait.hh" 68 69class BaseCPU; 70struct BaseCPUParams; 71class CheckerCPU; 72class ThreadContext; 73 74struct AddressMonitor 75{ 76 AddressMonitor(); 77 bool doMonitor(PacketPtr pkt); 78 79 bool armed; 80 Addr vAddr; 81 Addr pAddr; 82 uint64_t val; 83 bool waiting; // 0=normal, 1=mwaiting 84 bool gotWakeup; 85}; 86 87class CPUProgressEvent : public Event 88{ 89 protected: 90 Tick _interval; 91 Counter lastNumInst; 92 BaseCPU *cpu; 93 bool _repeatEvent; 94 95 public: 96 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 97 98 void process(); 99 100 void interval(Tick ival) { _interval = ival; } 101 Tick interval() { return _interval; } 102 103 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 104 105 virtual const char *description() const; 106}; 107 108class BaseCPU : public MemObject 109{ 110 protected: 111 112 // @todo remove me after debugging with legion done 113 Tick instCnt; 114 // every cpu has an id, put it in the base cpu 115 // Set at initialization, only time a cpuId might change is during a 116 // takeover (which should be done from within the BaseCPU anyway, 117 // therefore no setCpuId() method is provided 118 int _cpuId; 119 120 /** Each cpu will have a socket ID that corresponds to its physical location 121 * in the system. This is usually used to bucket cpu cores under single DVFS 122 * domain. This information may also be required by the OS to identify the 123 * cpu core grouping (as in the case of ARM via MPIDR register) 124 */ 125 const uint32_t _socketId; 126 127 /** instruction side request id that must be placed in all requests */ 128 MasterID _instMasterId; 129 130 /** data side request id that must be placed in all requests */ 131 MasterID _dataMasterId; 132 133 /** An intrenal representation of a task identifier within gem5. This is 134 * used so the CPU can add which taskId (which is an internal representation 135 * of the OS process ID) to each request so components in the memory system 136 * can track which process IDs are ultimately interacting with them 137 */ 138 uint32_t _taskId; 139 140 /** The current OS process ID that is executing on this processor. This is 141 * used to generate a taskId */ 142 uint32_t _pid; 143 144 /** Is the CPU switched out or active? */ 145 bool _switchedOut; 146 147 /** Cache the cache line size that we get from the system */ 148 const unsigned int _cacheLineSize; 149 150 public: 151 152 /** 153 * Purely virtual method that returns a reference to the data 154 * port. All subclasses must implement this method. 155 * 156 * @return a reference to the data port 157 */ 158 virtual MasterPort &getDataPort() = 0; 159 160 /** 161 * Purely virtual method that returns a reference to the instruction 162 * port. All subclasses must implement this method. 163 * 164 * @return a reference to the instruction port 165 */ 166 virtual MasterPort &getInstPort() = 0; 167 168 /** Reads this CPU's ID. */ 169 int cpuId() const { return _cpuId; } 170 171 /** Reads this CPU's Socket ID. */ 172 uint32_t socketId() const { return _socketId; } 173 174 /** Reads this CPU's unique data requestor ID */ 175 MasterID dataMasterId() { return _dataMasterId; } 176 /** Reads this CPU's unique instruction requestor ID */ 177 MasterID instMasterId() { return _instMasterId; } 178 179 /** 180 * Get a master port on this CPU. All CPUs have a data and 181 * instruction port, and this method uses getDataPort and 182 * getInstPort of the subclasses to resolve the two ports. 183 * 184 * @param if_name the port name 185 * @param idx ignored index 186 * 187 * @return a reference to the port with the given name 188 */ 189 BaseMasterPort &getMasterPort(const std::string &if_name, 190 PortID idx = InvalidPortID); 191 192 /** Get cpu task id */ 193 uint32_t taskId() const { return _taskId; } 194 /** Set cpu task id */ 195 void taskId(uint32_t id) { _taskId = id; } 196 197 uint32_t getPid() const { return _pid; } 198 void setPid(uint32_t pid) { _pid = pid; } 199 200 inline void workItemBegin() { numWorkItemsStarted++; } 201 inline void workItemEnd() { numWorkItemsCompleted++; } 202 // @todo remove me after debugging with legion done 203 Tick instCount() { return instCnt; } 204 205 TheISA::MicrocodeRom microcodeRom; 206 207 protected: 208 TheISA::Interrupts *interrupts; 209 210 public: 211 TheISA::Interrupts * 212 getInterruptController() 213 { 214 return interrupts; 215 } 216 217 virtual void wakeup() = 0; 218 219 void 220 postInterrupt(int int_num, int index) 221 { 222 interrupts->post(int_num, index); 223 if (FullSystem) 224 wakeup(); 225 } 226 227 void 228 clearInterrupt(int int_num, int index) 229 { 230 interrupts->clear(int_num, index); 231 } 232 233 void 234 clearInterrupts() 235 { 236 interrupts->clearAll(); 237 } 238 239 bool 240 checkInterrupts(ThreadContext *tc) const 241 { 242 return FullSystem && interrupts->checkInterrupts(tc); 243 } 244 245 class ProfileEvent : public Event 246 { 247 private: 248 BaseCPU *cpu; 249 Tick interval; 250 251 public: 252 ProfileEvent(BaseCPU *cpu, Tick interval); 253 void process(); 254 }; 255 ProfileEvent *profileEvent; 256 257 protected: 258 std::vector<ThreadContext *> threadContexts; 259 260 Trace::InstTracer * tracer; 261 262 public: 263 264 // Mask to align PCs to MachInst sized boundaries 265 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 266 267 /// Provide access to the tracer pointer 268 Trace::InstTracer * getTracer() { return tracer; } 269 270 /// Notify the CPU that the indicated context is now active. 271 virtual void activateContext(ThreadID thread_num) {} 272 273 /// Notify the CPU that the indicated context is now suspended. 274 virtual void suspendContext(ThreadID thread_num) {} 275 276 /// Notify the CPU that the indicated context is now halted. 277 virtual void haltContext(ThreadID thread_num) {} 278 279 /// Given a Thread Context pointer return the thread num 280 int findContext(ThreadContext *tc); 281 282 /// Given a thread num get tho thread context for it 283 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 284 285 /// Get the number of thread contexts available 286 unsigned numContexts() { return threadContexts.size(); } 287 288 public: 289 typedef BaseCPUParams Params; 290 const Params *params() const 291 { return reinterpret_cast<const Params *>(_params); } 292 BaseCPU(Params *params, bool is_checker = false); 293 virtual ~BaseCPU(); 294 295 virtual void init(); 296 virtual void startup(); 297 virtual void regStats(); 298 299 void regProbePoints() M5_ATTR_OVERRIDE; 300 301 void registerThreadContexts(); 302 303 /** 304 * Prepare for another CPU to take over execution. 305 * 306 * When this method exits, all internal state should have been 307 * flushed. After the method returns, the simulator calls 308 * takeOverFrom() on the new CPU with this CPU as its parameter. 309 */ 310 virtual void switchOut(); 311 312 /** 313 * Load the state of a CPU from the previous CPU object, invoked 314 * on all new CPUs that are about to be switched in. 315 * 316 * A CPU model implementing this method is expected to initialize 317 * its state from the old CPU and connect its memory (unless they 318 * are already connected) to the memories connected to the old 319 * CPU. 320 * 321 * @param cpu CPU to initialize read state from. 322 */ 323 virtual void takeOverFrom(BaseCPU *cpu); 324 325 /** 326 * Flush all TLBs in the CPU. 327 * 328 * This method is mainly used to flush stale translations when 329 * switching CPUs. It is also exported to the Python world to 330 * allow it to request a TLB flush after draining the CPU to make 331 * it easier to compare traces when debugging 332 * handover/checkpointing. 333 */ 334 void flushTLBs(); 335 336 /** 337 * Determine if the CPU is switched out. 338 * 339 * @return True if the CPU is switched out, false otherwise. 340 */ 341 bool switchedOut() const { return _switchedOut; } 342 343 /** 344 * Verify that the system is in a memory mode supported by the 345 * CPU. 346 * 347 * Implementations are expected to query the system for the 348 * current memory mode and ensure that it is what the CPU model 349 * expects. If the check fails, the implementation should 350 * terminate the simulation using fatal(). 351 */ 352 virtual void verifyMemoryMode() const { }; 353 354 /** 355 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 356 * This is a constant for the duration of the simulation. 357 */ 358 ThreadID numThreads; 359 360 /** 361 * Vector of per-thread instruction-based event queues. Used for 362 * scheduling events based on number of instructions committed by 363 * a particular thread. 364 */ 365 EventQueue **comInstEventQueue; 366 367 /** 368 * Vector of per-thread load-based event queues. Used for 369 * scheduling events based on number of loads committed by 370 *a particular thread. 371 */ 372 EventQueue **comLoadEventQueue; 373 374 System *system; 375 376 /** 377 * Get the cache line size of the system. 378 */ 379 inline unsigned int cacheLineSize() const { return _cacheLineSize; } 380 381 /** 382 * Serialize this object to the given output stream. 383 * 384 * @note CPU models should normally overload the serializeThread() 385 * method instead of the serialize() method as this provides a 386 * uniform data format for all CPU models and promotes better code 387 * reuse. 388 * 389 * @param os The stream to serialize to. 390 */ 391 virtual void serialize(std::ostream &os); 392 393 /** 394 * Reconstruct the state of this object from a checkpoint. 395 * 396 * @note CPU models should normally overload the 397 * unserializeThread() method instead of the unserialize() method 398 * as this provides a uniform data format for all CPU models and 399 * promotes better code reuse. 400 401 * @param cp The checkpoint use. 402 * @param section The section name of this object. 403 */ 404 virtual void unserialize(Checkpoint *cp, const std::string §ion); 405 406 /** 407 * Serialize a single thread. 408 * 409 * @param os The stream to serialize to. 410 * @param tid ID of the current thread. 411 */ 412 virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 413 414 /** 415 * Unserialize one thread. 416 * 417 * @param cp The checkpoint use. 418 * @param section The section name of this thread. 419 * @param tid ID of the current thread. 420 */ 421 virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 422 ThreadID tid) {}; 423 424 virtual Counter totalInsts() const = 0; 425 426 virtual Counter totalOps() const = 0; 427 428 /** 429 * Schedule an event that exits the simulation loops after a 430 * predefined number of instructions. 431 * 432 * This method is usually called from the configuration script to 433 * get an exit event some time in the future. It is typically used 434 * when the script wants to simulate for a specific number of 435 * instructions rather than ticks. 436 * 437 * @param tid Thread monitor. 438 * @param insts Number of instructions into the future. 439 * @param cause Cause to signal in the exit event. 440 */ 441 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 442 443 /** 444 * Schedule an event that exits the simulation loops after a 445 * predefined number of load operations. 446 * 447 * This method is usually called from the configuration script to 448 * get an exit event some time in the future. It is typically used 449 * when the script wants to simulate for a specific number of 450 * loads rather than ticks. 451 * 452 * @param tid Thread monitor. 453 * @param loads Number of load instructions into the future. 454 * @param cause Cause to signal in the exit event. 455 */ 456 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 457 458 public: 459 /** 460 * @{ 461 * @name PMU Probe points. 462 */ 463 464 /** 465 * Helper method to trigger PMU probes for a committed 466 * instruction. 467 * 468 * @param inst Instruction that just committed 469 */ 470 virtual void probeInstCommit(const StaticInstPtr &inst); 471 472 /** 473 * Helper method to instantiate probe points belonging to this 474 * object. 475 * 476 * @param name Name of the probe point. 477 * @return A unique_ptr to the new probe point. 478 */ 479 ProbePoints::PMUUPtr pmuProbePoint(const char *name); 480 481 /** CPU cycle counter */ 482 ProbePoints::PMUUPtr ppCycles; 483 484 /** 485 * Instruction commit probe point. 486 * 487 * This probe point is triggered whenever one or more instructions 488 * are committed. It is normally triggered once for every 489 * instruction. However, CPU models committing bundles of 490 * instructions may call notify once for the entire bundle. 491 */ 492 ProbePoints::PMUUPtr ppRetiredInsts; 493 494 /** Retired load instructions */ 495 ProbePoints::PMUUPtr ppRetiredLoads; 496 /** Retired store instructions */ 497 ProbePoints::PMUUPtr ppRetiredStores; 498 499 /** Retired branches (any type) */ 500 ProbePoints::PMUUPtr ppRetiredBranches; 501 502 /** @} */ 503 504 505 506 // Function tracing 507 private: 508 bool functionTracingEnabled; 509 std::ostream *functionTraceStream; 510 Addr currentFunctionStart; 511 Addr currentFunctionEnd; 512 Tick functionEntryTick; 513 void enableFunctionTrace(); 514 void traceFunctionsInternal(Addr pc); 515 516 private: 517 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 518 519 public: 520 void traceFunctions(Addr pc) 521 { 522 if (functionTracingEnabled) 523 traceFunctionsInternal(pc); 524 } 525 526 static int numSimulatedCPUs() { return cpuList.size(); } 527 static Counter numSimulatedInsts() 528 { 529 Counter total = 0; 530 531 int size = cpuList.size(); 532 for (int i = 0; i < size; ++i) 533 total += cpuList[i]->totalInsts(); 534 535 return total; 536 } 537 538 static Counter numSimulatedOps() 539 { 540 Counter total = 0; 541 542 int size = cpuList.size(); 543 for (int i = 0; i < size; ++i) 544 total += cpuList[i]->totalOps(); 545 546 return total; 547 } 548 549 public: 550 // Number of CPU cycles simulated 551 Stats::Scalar numCycles; 552 Stats::Scalar numWorkItemsStarted; 553 Stats::Scalar numWorkItemsCompleted; 554 555 private: 556 AddressMonitor addressMonitor; 557 558 public: 559 void armMonitor(Addr address); 560 bool mwait(PacketPtr pkt); 561 void mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb); 562 AddressMonitor *getCpuAddrMonitor() { return &addressMonitor; } 563 void atomicNotify(Addr address); 564}; 565 566#endif // THE_ISA == NULL_ISA 567 568#endif // __CPU_BASE_HH__ 569