base.hh revision 10407
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#ifndef __CPU_BASE_HH__ 47#define __CPU_BASE_HH__ 48 49#include <vector> 50 51// Before we do anything else, check if this build is the NULL ISA, 52// and if so stop here 53#include "config/the_isa.hh" 54#if THE_ISA == NULL_ISA 55#include "arch/null/cpu_dummy.hh" 56#else 57#include "arch/interrupts.hh" 58#include "arch/isa_traits.hh" 59#include "arch/microcode_rom.hh" 60#include "base/statistics.hh" 61#include "mem/mem_object.hh" 62#include "sim/eventq.hh" 63#include "sim/full_system.hh" 64#include "sim/insttracer.hh" 65#include "sim/system.hh" 66 67struct BaseCPUParams; 68class CheckerCPU; 69class ThreadContext; 70 71class CPUProgressEvent : public Event 72{ 73 protected: 74 Tick _interval; 75 Counter lastNumInst; 76 BaseCPU *cpu; 77 bool _repeatEvent; 78 79 public: 80 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 81 82 void process(); 83 84 void interval(Tick ival) { _interval = ival; } 85 Tick interval() { return _interval; } 86 87 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 88 89 virtual const char *description() const; 90}; 91 92class BaseCPU : public MemObject 93{ 94 protected: 95 96 // @todo remove me after debugging with legion done 97 Tick instCnt; 98 // every cpu has an id, put it in the base cpu 99 // Set at initialization, only time a cpuId might change is during a 100 // takeover (which should be done from within the BaseCPU anyway, 101 // therefore no setCpuId() method is provided 102 int _cpuId; 103 104 /** Each cpu will have a socket ID that corresponds to its physical location 105 * in the system. This is usually used to bucket cpu cores under single DVFS 106 * domain. This information may also be required by the OS to identify the 107 * cpu core grouping (as in the case of ARM via MPIDR register) 108 */ 109 const uint32_t _socketId; 110 111 /** instruction side request id that must be placed in all requests */ 112 MasterID _instMasterId; 113 114 /** data side request id that must be placed in all requests */ 115 MasterID _dataMasterId; 116 117 /** An intrenal representation of a task identifier within gem5. This is 118 * used so the CPU can add which taskId (which is an internal representation 119 * of the OS process ID) to each request so components in the memory system 120 * can track which process IDs are ultimately interacting with them 121 */ 122 uint32_t _taskId; 123 124 /** The current OS process ID that is executing on this processor. This is 125 * used to generate a taskId */ 126 uint32_t _pid; 127 128 /** Is the CPU switched out or active? */ 129 bool _switchedOut; 130 131 /** Cache the cache line size that we get from the system */ 132 const unsigned int _cacheLineSize; 133 134 public: 135 136 /** 137 * Purely virtual method that returns a reference to the data 138 * port. All subclasses must implement this method. 139 * 140 * @return a reference to the data port 141 */ 142 virtual MasterPort &getDataPort() = 0; 143 144 /** 145 * Purely virtual method that returns a reference to the instruction 146 * port. All subclasses must implement this method. 147 * 148 * @return a reference to the instruction port 149 */ 150 virtual MasterPort &getInstPort() = 0; 151 152 /** Reads this CPU's ID. */ 153 int cpuId() const { return _cpuId; } 154 155 /** Reads this CPU's Socket ID. */ 156 uint32_t socketId() const { return _socketId; } 157 158 /** Reads this CPU's unique data requestor ID */ 159 MasterID dataMasterId() { return _dataMasterId; } 160 /** Reads this CPU's unique instruction requestor ID */ 161 MasterID instMasterId() { return _instMasterId; } 162 163 /** 164 * Get a master port on this CPU. All CPUs have a data and 165 * instruction port, and this method uses getDataPort and 166 * getInstPort of the subclasses to resolve the two ports. 167 * 168 * @param if_name the port name 169 * @param idx ignored index 170 * 171 * @return a reference to the port with the given name 172 */ 173 BaseMasterPort &getMasterPort(const std::string &if_name, 174 PortID idx = InvalidPortID); 175 176 /** Get cpu task id */ 177 uint32_t taskId() const { return _taskId; } 178 /** Set cpu task id */ 179 void taskId(uint32_t id) { _taskId = id; } 180 181 uint32_t getPid() const { return _pid; } 182 void setPid(uint32_t pid) { _pid = pid; } 183 184 inline void workItemBegin() { numWorkItemsStarted++; } 185 inline void workItemEnd() { numWorkItemsCompleted++; } 186 // @todo remove me after debugging with legion done 187 Tick instCount() { return instCnt; } 188 189 TheISA::MicrocodeRom microcodeRom; 190 191 protected: 192 TheISA::Interrupts *interrupts; 193 194 public: 195 TheISA::Interrupts * 196 getInterruptController() 197 { 198 return interrupts; 199 } 200 201 virtual void wakeup() = 0; 202 203 void 204 postInterrupt(int int_num, int index) 205 { 206 interrupts->post(int_num, index); 207 if (FullSystem) 208 wakeup(); 209 } 210 211 void 212 clearInterrupt(int int_num, int index) 213 { 214 interrupts->clear(int_num, index); 215 } 216 217 void 218 clearInterrupts() 219 { 220 interrupts->clearAll(); 221 } 222 223 bool 224 checkInterrupts(ThreadContext *tc) const 225 { 226 return FullSystem && interrupts->checkInterrupts(tc); 227 } 228 229 class ProfileEvent : public Event 230 { 231 private: 232 BaseCPU *cpu; 233 Tick interval; 234 235 public: 236 ProfileEvent(BaseCPU *cpu, Tick interval); 237 void process(); 238 }; 239 ProfileEvent *profileEvent; 240 241 protected: 242 std::vector<ThreadContext *> threadContexts; 243 244 Trace::InstTracer * tracer; 245 246 public: 247 248 // Mask to align PCs to MachInst sized boundaries 249 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 250 251 /// Provide access to the tracer pointer 252 Trace::InstTracer * getTracer() { return tracer; } 253 254 /// Notify the CPU that the indicated context is now active. 255 virtual void activateContext(ThreadID thread_num) {} 256 257 /// Notify the CPU that the indicated context is now suspended. 258 virtual void suspendContext(ThreadID thread_num) {} 259 260 /// Notify the CPU that the indicated context is now deallocated. 261 virtual void deallocateContext(ThreadID thread_num) {} 262 263 /// Notify the CPU that the indicated context is now halted. 264 virtual void haltContext(ThreadID thread_num) {} 265 266 /// Given a Thread Context pointer return the thread num 267 int findContext(ThreadContext *tc); 268 269 /// Given a thread num get tho thread context for it 270 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 271 272 /// Get the number of thread contexts available 273 unsigned numContexts() { return threadContexts.size(); } 274 275 public: 276 typedef BaseCPUParams Params; 277 const Params *params() const 278 { return reinterpret_cast<const Params *>(_params); } 279 BaseCPU(Params *params, bool is_checker = false); 280 virtual ~BaseCPU(); 281 282 virtual void init(); 283 virtual void startup(); 284 virtual void regStats(); 285 286 void registerThreadContexts(); 287 288 /** 289 * Prepare for another CPU to take over execution. 290 * 291 * When this method exits, all internal state should have been 292 * flushed. After the method returns, the simulator calls 293 * takeOverFrom() on the new CPU with this CPU as its parameter. 294 */ 295 virtual void switchOut(); 296 297 /** 298 * Load the state of a CPU from the previous CPU object, invoked 299 * on all new CPUs that are about to be switched in. 300 * 301 * A CPU model implementing this method is expected to initialize 302 * its state from the old CPU and connect its memory (unless they 303 * are already connected) to the memories connected to the old 304 * CPU. 305 * 306 * @param cpu CPU to initialize read state from. 307 */ 308 virtual void takeOverFrom(BaseCPU *cpu); 309 310 /** 311 * Flush all TLBs in the CPU. 312 * 313 * This method is mainly used to flush stale translations when 314 * switching CPUs. It is also exported to the Python world to 315 * allow it to request a TLB flush after draining the CPU to make 316 * it easier to compare traces when debugging 317 * handover/checkpointing. 318 */ 319 void flushTLBs(); 320 321 /** 322 * Determine if the CPU is switched out. 323 * 324 * @return True if the CPU is switched out, false otherwise. 325 */ 326 bool switchedOut() const { return _switchedOut; } 327 328 /** 329 * Verify that the system is in a memory mode supported by the 330 * CPU. 331 * 332 * Implementations are expected to query the system for the 333 * current memory mode and ensure that it is what the CPU model 334 * expects. If the check fails, the implementation should 335 * terminate the simulation using fatal(). 336 */ 337 virtual void verifyMemoryMode() const { }; 338 339 /** 340 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 341 * This is a constant for the duration of the simulation. 342 */ 343 ThreadID numThreads; 344 345 /** 346 * Vector of per-thread instruction-based event queues. Used for 347 * scheduling events based on number of instructions committed by 348 * a particular thread. 349 */ 350 EventQueue **comInstEventQueue; 351 352 /** 353 * Vector of per-thread load-based event queues. Used for 354 * scheduling events based on number of loads committed by 355 *a particular thread. 356 */ 357 EventQueue **comLoadEventQueue; 358 359 System *system; 360 361 /** 362 * Get the cache line size of the system. 363 */ 364 inline unsigned int cacheLineSize() const { return _cacheLineSize; } 365 366 /** 367 * Serialize this object to the given output stream. 368 * 369 * @note CPU models should normally overload the serializeThread() 370 * method instead of the serialize() method as this provides a 371 * uniform data format for all CPU models and promotes better code 372 * reuse. 373 * 374 * @param os The stream to serialize to. 375 */ 376 virtual void serialize(std::ostream &os); 377 378 /** 379 * Reconstruct the state of this object from a checkpoint. 380 * 381 * @note CPU models should normally overload the 382 * unserializeThread() method instead of the unserialize() method 383 * as this provides a uniform data format for all CPU models and 384 * promotes better code reuse. 385 386 * @param cp The checkpoint use. 387 * @param section The section name of this object. 388 */ 389 virtual void unserialize(Checkpoint *cp, const std::string §ion); 390 391 /** 392 * Serialize a single thread. 393 * 394 * @param os The stream to serialize to. 395 * @param tid ID of the current thread. 396 */ 397 virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 398 399 /** 400 * Unserialize one thread. 401 * 402 * @param cp The checkpoint use. 403 * @param section The section name of this thread. 404 * @param tid ID of the current thread. 405 */ 406 virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 407 ThreadID tid) {}; 408 409 virtual Counter totalInsts() const = 0; 410 411 virtual Counter totalOps() const = 0; 412 413 /** 414 * Schedule an event that exits the simulation loops after a 415 * predefined number of instructions. 416 * 417 * This method is usually called from the configuration script to 418 * get an exit event some time in the future. It is typically used 419 * when the script wants to simulate for a specific number of 420 * instructions rather than ticks. 421 * 422 * @param tid Thread monitor. 423 * @param insts Number of instructions into the future. 424 * @param cause Cause to signal in the exit event. 425 */ 426 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 427 428 /** 429 * Schedule an event that exits the simulation loops after a 430 * predefined number of load operations. 431 * 432 * This method is usually called from the configuration script to 433 * get an exit event some time in the future. It is typically used 434 * when the script wants to simulate for a specific number of 435 * loads rather than ticks. 436 * 437 * @param tid Thread monitor. 438 * @param loads Number of load instructions into the future. 439 * @param cause Cause to signal in the exit event. 440 */ 441 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 442 443 // Function tracing 444 private: 445 bool functionTracingEnabled; 446 std::ostream *functionTraceStream; 447 Addr currentFunctionStart; 448 Addr currentFunctionEnd; 449 Tick functionEntryTick; 450 void enableFunctionTrace(); 451 void traceFunctionsInternal(Addr pc); 452 453 private: 454 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 455 456 public: 457 void traceFunctions(Addr pc) 458 { 459 if (functionTracingEnabled) 460 traceFunctionsInternal(pc); 461 } 462 463 static int numSimulatedCPUs() { return cpuList.size(); } 464 static Counter numSimulatedInsts() 465 { 466 Counter total = 0; 467 468 int size = cpuList.size(); 469 for (int i = 0; i < size; ++i) 470 total += cpuList[i]->totalInsts(); 471 472 return total; 473 } 474 475 static Counter numSimulatedOps() 476 { 477 Counter total = 0; 478 479 int size = cpuList.size(); 480 for (int i = 0; i < size; ++i) 481 total += cpuList[i]->totalOps(); 482 483 return total; 484 } 485 486 public: 487 // Number of CPU cycles simulated 488 Stats::Scalar numCycles; 489 Stats::Scalar numWorkItemsStarted; 490 Stats::Scalar numWorkItemsCompleted; 491}; 492 493#endif // THE_ISA == NULL_ISA 494 495#endif // __CPU_BASE_HH__ 496