base.hh revision 9749
12SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 54707SN/A#include "base/statistics.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 602SN/A 618901Sandreas.hansson@arm.comstruct BaseCPUParams; 622190SN/Aclass BranchPred; 632315SN/Aclass CheckerCPU; 642680Sktlim@umich.educlass ThreadContext; 652SN/Aclass System; 662SN/A 672356SN/Aclass CPUProgressEvent : public Event 682356SN/A{ 692356SN/A protected: 706144Sksewell@umich.edu Tick _interval; 712356SN/A Counter lastNumInst; 722356SN/A BaseCPU *cpu; 736144Sksewell@umich.edu bool _repeatEvent; 742356SN/A 752356SN/A public: 766144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 772356SN/A 782356SN/A void process(); 792356SN/A 806144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 816144Sksewell@umich.edu Tick interval() { return _interval; } 826144Sksewell@umich.edu 836144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 846144Sksewell@umich.edu 855336Shines@cs.fsu.edu virtual const char *description() const; 862356SN/A}; 872356SN/A 882856Srdreslin@umich.educlass BaseCPU : public MemObject 892SN/A{ 901634SN/A protected: 919157Sandreas.hansson@arm.com 923814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 933814Ssaidi@eecs.umich.edu Tick instCnt; 945712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 955712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 965715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 975712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 985712Shsul@eecs.umich.edu int _cpuId; 991634SN/A 1008832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1018832SAli.Saidi@ARM.com MasterID _instMasterId; 1028832SAli.Saidi@ARM.com 1038832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1048832SAli.Saidi@ARM.com MasterID _dataMasterId; 1058832SAli.Saidi@ARM.com 1069332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1079332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1089332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1099332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1109332Sdam.sunwoo@arm.com */ 1119332Sdam.sunwoo@arm.com uint32_t _taskId; 1129332Sdam.sunwoo@arm.com 1139332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1149332Sdam.sunwoo@arm.com * used to generate a taskId */ 1159332Sdam.sunwoo@arm.com uint32_t _pid; 1169332Sdam.sunwoo@arm.com 1179430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1189430SAndreas.Sandberg@ARM.com bool _switchedOut; 1199430SAndreas.Sandberg@ARM.com 1201634SN/A public: 1218850Sandreas.hansson@arm.com 1228850Sandreas.hansson@arm.com /** 1238850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1248850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1258850Sandreas.hansson@arm.com * 1268850Sandreas.hansson@arm.com * @return a reference to the data port 1278850Sandreas.hansson@arm.com */ 1289608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1298850Sandreas.hansson@arm.com 1308850Sandreas.hansson@arm.com /** 1318850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1328850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1338850Sandreas.hansson@arm.com * 1348850Sandreas.hansson@arm.com * @return a reference to the instruction port 1358850Sandreas.hansson@arm.com */ 1369608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1378850Sandreas.hansson@arm.com 1385712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1395712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1405712Shsul@eecs.umich.edu 1418832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1428832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1438832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1448832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1458832SAli.Saidi@ARM.com 1468850Sandreas.hansson@arm.com /** 1478926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1488926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1498926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1508850Sandreas.hansson@arm.com * 1518850Sandreas.hansson@arm.com * @param if_name the port name 1528850Sandreas.hansson@arm.com * @param idx ignored index 1538850Sandreas.hansson@arm.com * 1548922Swilliam.wang@arm.com * @return a reference to the port with the given name 1558850Sandreas.hansson@arm.com */ 1569294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1579294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1588850Sandreas.hansson@arm.com 1599332Sdam.sunwoo@arm.com /** Get cpu task id */ 1609332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1619332Sdam.sunwoo@arm.com /** Set cpu task id */ 1629332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1639332Sdam.sunwoo@arm.com 1649332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 1659332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 1669332Sdam.sunwoo@arm.com 1677914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1687914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1693814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1703814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1711634SN/A 1725664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1735664Sgblack@eecs.umich.edu 1742SN/A protected: 1755704Snate@binkert.org TheISA::Interrupts *interrupts; 1762SN/A 1772SN/A public: 1785645Sgblack@eecs.umich.edu TheISA::Interrupts * 1795645Sgblack@eecs.umich.edu getInterruptController() 1805645Sgblack@eecs.umich.edu { 1815647Sgblack@eecs.umich.edu return interrupts; 1825645Sgblack@eecs.umich.edu } 1835645Sgblack@eecs.umich.edu 1845807Snate@binkert.org virtual void wakeup() = 0; 1855807Snate@binkert.org 1865807Snate@binkert.org void 1875807Snate@binkert.org postInterrupt(int int_num, int index) 1885807Snate@binkert.org { 1895807Snate@binkert.org interrupts->post(int_num, index); 1908779Sgblack@eecs.umich.edu if (FullSystem) 1918779Sgblack@eecs.umich.edu wakeup(); 1925807Snate@binkert.org } 1935807Snate@binkert.org 1945807Snate@binkert.org void 1955807Snate@binkert.org clearInterrupt(int int_num, int index) 1965807Snate@binkert.org { 1975807Snate@binkert.org interrupts->clear(int_num, index); 1985807Snate@binkert.org } 1995807Snate@binkert.org 2005807Snate@binkert.org void 2015807Snate@binkert.org clearInterrupts() 2025807Snate@binkert.org { 2035807Snate@binkert.org interrupts->clearAll(); 2045807Snate@binkert.org } 2052SN/A 2065704Snate@binkert.org bool 2075704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2085704Snate@binkert.org { 2098793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2105704Snate@binkert.org } 2111917SN/A 2121917SN/A class ProfileEvent : public Event 2131917SN/A { 2141917SN/A private: 2151917SN/A BaseCPU *cpu; 2165536Srstrong@hp.com Tick interval; 2171917SN/A 2181917SN/A public: 2195536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2201917SN/A void process(); 2211917SN/A }; 2221917SN/A ProfileEvent *profileEvent; 2232SN/A 2242SN/A protected: 2252680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2262SN/A 2274776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2284776Sgblack@eecs.umich.edu 2292SN/A public: 230393SN/A 2317764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2327764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2337764Sgblack@eecs.umich.edu 2344776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2354776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2364776Sgblack@eecs.umich.edu 237393SN/A /// Notify the CPU that the indicated context is now active. The 238393SN/A /// delay parameter indicates the number of ticks to wait before 239393SN/A /// executing (typically 0 or 1). 2409180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay) {} 241393SN/A 242393SN/A /// Notify the CPU that the indicated context is now suspended. 2438737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 244393SN/A 245393SN/A /// Notify the CPU that the indicated context is now deallocated. 2468737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 247393SN/A 248393SN/A /// Notify the CPU that the indicated context is now halted. 2498737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2502SN/A 2514000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2524000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2534000Ssaidi@eecs.umich.edu 2544000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2559652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2564000Ssaidi@eecs.umich.edu 2572SN/A public: 2585529Snate@binkert.org typedef BaseCPUParams Params; 2595529Snate@binkert.org const Params *params() const 2605529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2618876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2621191SN/A virtual ~BaseCPU(); 2632SN/A 2641129SN/A virtual void init(); 2651917SN/A virtual void startup(); 2662SN/A virtual void regStats(); 2672SN/A 2686221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2692103SN/A 2702680Sktlim@umich.edu void registerThreadContexts(); 271180SN/A 2729254SAndreas.Sandberg@arm.com /** 2739254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 2749254SAndreas.Sandberg@arm.com * 2759254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 2769254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 2779254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 2789254SAndreas.Sandberg@arm.com */ 2792798Sktlim@umich.edu virtual void switchOut(); 280180SN/A 2819254SAndreas.Sandberg@arm.com /** 2829254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 2839254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 2849254SAndreas.Sandberg@arm.com * 2859254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 2869254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 2879254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 2889254SAndreas.Sandberg@arm.com * CPU. 2899254SAndreas.Sandberg@arm.com * 2909254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 2919254SAndreas.Sandberg@arm.com */ 2929254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 293180SN/A 294124SN/A /** 2959446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 2969446SAndreas.Sandberg@ARM.com * 2979446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 2989446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 2999446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3009446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3019446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3029446SAndreas.Sandberg@ARM.com */ 3039446SAndreas.Sandberg@ARM.com void flushTLBs(); 3049446SAndreas.Sandberg@ARM.com 3059446SAndreas.Sandberg@ARM.com /** 3069430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3079430SAndreas.Sandberg@ARM.com * 3089430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3099430SAndreas.Sandberg@ARM.com */ 3109430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3119430SAndreas.Sandberg@ARM.com 3129430SAndreas.Sandberg@ARM.com /** 3139523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3149523SAndreas.Sandberg@ARM.com * CPU. 3159523SAndreas.Sandberg@ARM.com * 3169523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3179523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3189523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3199523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3209523SAndreas.Sandberg@ARM.com */ 3219523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3229523SAndreas.Sandberg@ARM.com 3239523SAndreas.Sandberg@ARM.com /** 324124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 325124SN/A * This is a constant for the duration of the simulation. 326124SN/A */ 3276221Snate@binkert.org ThreadID numThreads; 3282SN/A 329124SN/A /** 330124SN/A * Vector of per-thread instruction-based event queues. Used for 331124SN/A * scheduling events based on number of instructions committed by 332124SN/A * a particular thread. 333124SN/A */ 334503SN/A EventQueue **comInstEventQueue; 3352SN/A 336124SN/A /** 337124SN/A * Vector of per-thread load-based event queues. Used for 338124SN/A * scheduling events based on number of loads committed by 339124SN/A *a particular thread. 340124SN/A */ 341124SN/A EventQueue **comLoadEventQueue; 342124SN/A 3432SN/A System *system; 344921SN/A 345921SN/A /** 346921SN/A * Serialize this object to the given output stream. 3479448SAndreas.Sandberg@ARM.com * 3489448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 3499448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 3509448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 3519448SAndreas.Sandberg@ARM.com * reuse. 3529448SAndreas.Sandberg@ARM.com * 353921SN/A * @param os The stream to serialize to. 354921SN/A */ 355921SN/A virtual void serialize(std::ostream &os); 356921SN/A 357921SN/A /** 358921SN/A * Reconstruct the state of this object from a checkpoint. 3599448SAndreas.Sandberg@ARM.com * 3609448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 3619448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 3629448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 3639448SAndreas.Sandberg@ARM.com * promotes better code reuse. 3649448SAndreas.Sandberg@ARM.com 365921SN/A * @param cp The checkpoint use. 3669448SAndreas.Sandberg@ARM.com * @param section The section name of this object. 367921SN/A */ 368921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 369921SN/A 370124SN/A /** 3719448SAndreas.Sandberg@ARM.com * Serialize a single thread. 3729448SAndreas.Sandberg@ARM.com * 3739448SAndreas.Sandberg@ARM.com * @param os The stream to serialize to. 3749448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 3759448SAndreas.Sandberg@ARM.com */ 3769448SAndreas.Sandberg@ARM.com virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 3779448SAndreas.Sandberg@ARM.com 3789448SAndreas.Sandberg@ARM.com /** 3799448SAndreas.Sandberg@ARM.com * Unserialize one thread. 3809448SAndreas.Sandberg@ARM.com * 3819448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 3829448SAndreas.Sandberg@ARM.com * @param section The section name of this thread. 3839448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 3849448SAndreas.Sandberg@ARM.com */ 3859448SAndreas.Sandberg@ARM.com virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 3869448SAndreas.Sandberg@ARM.com ThreadID tid) {}; 3879448SAndreas.Sandberg@ARM.com 3889448SAndreas.Sandberg@ARM.com /** 389124SN/A * Return pointer to CPU's branch predictor (NULL if none). 390124SN/A * @return Branch predictor pointer. 391124SN/A */ 3922SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3932SN/A 3948834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 3958834Satgutier@umich.edu 3968834Satgutier@umich.edu virtual Counter totalOps() const = 0; 397707SN/A 3989749Sandreas@sandberg.pp.se /** 3999749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4009749Sandreas@sandberg.pp.se * predefined number of instructions. 4019749Sandreas@sandberg.pp.se * 4029749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4039749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4049749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4059749Sandreas@sandberg.pp.se * instructions rather than ticks. 4069749Sandreas@sandberg.pp.se * 4079749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4089749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4099749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4109749Sandreas@sandberg.pp.se */ 4119749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4129749Sandreas@sandberg.pp.se 4139749Sandreas@sandberg.pp.se /** 4149749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4159749Sandreas@sandberg.pp.se * predefined number of load operations. 4169749Sandreas@sandberg.pp.se * 4179749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4189749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4199749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4209749Sandreas@sandberg.pp.se * loads rather than ticks. 4219749Sandreas@sandberg.pp.se * 4229749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4239749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4249749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4259749Sandreas@sandberg.pp.se */ 4269749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4279749Sandreas@sandberg.pp.se 4281191SN/A // Function tracing 4291191SN/A private: 4301191SN/A bool functionTracingEnabled; 4311191SN/A std::ostream *functionTraceStream; 4321191SN/A Addr currentFunctionStart; 4331191SN/A Addr currentFunctionEnd; 4341191SN/A Tick functionEntryTick; 4351191SN/A void enableFunctionTrace(); 4361191SN/A void traceFunctionsInternal(Addr pc); 4371191SN/A 4388662SAli.Saidi@ARM.com private: 4398662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 4408662SAli.Saidi@ARM.com 4418662SAli.Saidi@ARM.com public: 4421191SN/A void traceFunctions(Addr pc) 4431191SN/A { 4441191SN/A if (functionTracingEnabled) 4451191SN/A traceFunctionsInternal(pc); 4461191SN/A } 4471191SN/A 4482SN/A static int numSimulatedCPUs() { return cpuList.size(); } 4498834Satgutier@umich.edu static Counter numSimulatedInsts() 450707SN/A { 451707SN/A Counter total = 0; 452707SN/A 453707SN/A int size = cpuList.size(); 454707SN/A for (int i = 0; i < size; ++i) 4558834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 4568834Satgutier@umich.edu 4578834Satgutier@umich.edu return total; 4588834Satgutier@umich.edu } 4598834Satgutier@umich.edu 4608834Satgutier@umich.edu static Counter numSimulatedOps() 4618834Satgutier@umich.edu { 4628834Satgutier@umich.edu Counter total = 0; 4638834Satgutier@umich.edu 4648834Satgutier@umich.edu int size = cpuList.size(); 4658834Satgutier@umich.edu for (int i = 0; i < size; ++i) 4668834Satgutier@umich.edu total += cpuList[i]->totalOps(); 467707SN/A 468707SN/A return total; 469707SN/A } 470707SN/A 471707SN/A public: 472707SN/A // Number of CPU cycles simulated 4735999Snate@binkert.org Stats::Scalar numCycles; 4747914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 4757914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 4762SN/A}; 4772SN/A 4781717SN/A#endif // __CPU_BASE_HH__ 479