base.hh revision 9446
12SN/A/* 29430SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 54707SN/A#include "base/statistics.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 602SN/A 618901Sandreas.hansson@arm.comstruct BaseCPUParams; 622190SN/Aclass BranchPred; 632315SN/Aclass CheckerCPU; 642680Sktlim@umich.educlass ThreadContext; 652SN/Aclass System; 662SN/A 672356SN/Aclass CPUProgressEvent : public Event 682356SN/A{ 692356SN/A protected: 706144Sksewell@umich.edu Tick _interval; 712356SN/A Counter lastNumInst; 722356SN/A BaseCPU *cpu; 736144Sksewell@umich.edu bool _repeatEvent; 742356SN/A 752356SN/A public: 766144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 772356SN/A 782356SN/A void process(); 792356SN/A 806144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 816144Sksewell@umich.edu Tick interval() { return _interval; } 826144Sksewell@umich.edu 836144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 846144Sksewell@umich.edu 855336Shines@cs.fsu.edu virtual const char *description() const; 862356SN/A}; 872356SN/A 882856Srdreslin@umich.educlass BaseCPU : public MemObject 892SN/A{ 901634SN/A protected: 919157Sandreas.hansson@arm.com 923814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 933814Ssaidi@eecs.umich.edu Tick instCnt; 945712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 955712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 965715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 975712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 985712Shsul@eecs.umich.edu int _cpuId; 991634SN/A 1008832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1018832SAli.Saidi@ARM.com MasterID _instMasterId; 1028832SAli.Saidi@ARM.com 1038832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1048832SAli.Saidi@ARM.com MasterID _dataMasterId; 1058832SAli.Saidi@ARM.com 1069332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1079332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1089332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1099332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1109332Sdam.sunwoo@arm.com */ 1119332Sdam.sunwoo@arm.com uint32_t _taskId; 1129332Sdam.sunwoo@arm.com 1139332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1149332Sdam.sunwoo@arm.com * used to generate a taskId */ 1159332Sdam.sunwoo@arm.com uint32_t _pid; 1169332Sdam.sunwoo@arm.com 1179430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1189430SAndreas.Sandberg@ARM.com bool _switchedOut; 1199430SAndreas.Sandberg@ARM.com 1208707Sandreas.hansson@arm.com /** 1218707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1228707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1238707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1248707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1258707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1268707Sandreas.hansson@arm.com * subclasses have to override these methods. 1278707Sandreas.hansson@arm.com */ 1288922Swilliam.wang@arm.com class CpuPort : public MasterPort 1298707Sandreas.hansson@arm.com { 1308707Sandreas.hansson@arm.com public: 1318707Sandreas.hansson@arm.com 1328707Sandreas.hansson@arm.com /** 1338707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1348707Sandreas.hansson@arm.com * 1358707Sandreas.hansson@arm.com * @param _name port name including the owner 1368707Sandreas.hansson@arm.com * @param _name structural owner of this port 1378707Sandreas.hansson@arm.com */ 1388707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1398922Swilliam.wang@arm.com MasterPort(_name, _owner) 1408707Sandreas.hansson@arm.com { } 1418707Sandreas.hansson@arm.com 1428707Sandreas.hansson@arm.com protected: 1438707Sandreas.hansson@arm.com 1448975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1458707Sandreas.hansson@arm.com 1468707Sandreas.hansson@arm.com virtual void recvRetry(); 1478707Sandreas.hansson@arm.com 1488948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1498707Sandreas.hansson@arm.com 1508707Sandreas.hansson@arm.com }; 1518707Sandreas.hansson@arm.com 1521634SN/A public: 1538850Sandreas.hansson@arm.com 1548850Sandreas.hansson@arm.com /** 1558850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1568850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1578850Sandreas.hansson@arm.com * 1588850Sandreas.hansson@arm.com * @return a reference to the data port 1598850Sandreas.hansson@arm.com */ 1608850Sandreas.hansson@arm.com virtual CpuPort &getDataPort() = 0; 1618850Sandreas.hansson@arm.com 1628850Sandreas.hansson@arm.com /** 1638850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1648850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1658850Sandreas.hansson@arm.com * 1668850Sandreas.hansson@arm.com * @return a reference to the instruction port 1678850Sandreas.hansson@arm.com */ 1688850Sandreas.hansson@arm.com virtual CpuPort &getInstPort() = 0; 1698850Sandreas.hansson@arm.com 1705712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1715712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1725712Shsul@eecs.umich.edu 1738832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1748832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1758832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1768832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1778832SAli.Saidi@ARM.com 1788850Sandreas.hansson@arm.com /** 1798926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1808926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1818926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1828850Sandreas.hansson@arm.com * 1838850Sandreas.hansson@arm.com * @param if_name the port name 1848850Sandreas.hansson@arm.com * @param idx ignored index 1858850Sandreas.hansson@arm.com * 1868922Swilliam.wang@arm.com * @return a reference to the port with the given name 1878850Sandreas.hansson@arm.com */ 1889294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1899294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1908850Sandreas.hansson@arm.com 1919332Sdam.sunwoo@arm.com /** Get cpu task id */ 1929332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1939332Sdam.sunwoo@arm.com /** Set cpu task id */ 1949332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1959332Sdam.sunwoo@arm.com 1969332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 1979332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 1989332Sdam.sunwoo@arm.com 1997914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 2007914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 2013814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 2023814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 2031634SN/A 2045664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2055664Sgblack@eecs.umich.edu 2062SN/A protected: 2075704Snate@binkert.org TheISA::Interrupts *interrupts; 2082SN/A 2092SN/A public: 2105645Sgblack@eecs.umich.edu TheISA::Interrupts * 2115645Sgblack@eecs.umich.edu getInterruptController() 2125645Sgblack@eecs.umich.edu { 2135647Sgblack@eecs.umich.edu return interrupts; 2145645Sgblack@eecs.umich.edu } 2155645Sgblack@eecs.umich.edu 2165807Snate@binkert.org virtual void wakeup() = 0; 2175807Snate@binkert.org 2185807Snate@binkert.org void 2195807Snate@binkert.org postInterrupt(int int_num, int index) 2205807Snate@binkert.org { 2215807Snate@binkert.org interrupts->post(int_num, index); 2228779Sgblack@eecs.umich.edu if (FullSystem) 2238779Sgblack@eecs.umich.edu wakeup(); 2245807Snate@binkert.org } 2255807Snate@binkert.org 2265807Snate@binkert.org void 2275807Snate@binkert.org clearInterrupt(int int_num, int index) 2285807Snate@binkert.org { 2295807Snate@binkert.org interrupts->clear(int_num, index); 2305807Snate@binkert.org } 2315807Snate@binkert.org 2325807Snate@binkert.org void 2335807Snate@binkert.org clearInterrupts() 2345807Snate@binkert.org { 2355807Snate@binkert.org interrupts->clearAll(); 2365807Snate@binkert.org } 2372SN/A 2385704Snate@binkert.org bool 2395704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2405704Snate@binkert.org { 2418793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2425704Snate@binkert.org } 2431917SN/A 2441917SN/A class ProfileEvent : public Event 2451917SN/A { 2461917SN/A private: 2471917SN/A BaseCPU *cpu; 2485536Srstrong@hp.com Tick interval; 2491917SN/A 2501917SN/A public: 2515536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2521917SN/A void process(); 2531917SN/A }; 2541917SN/A ProfileEvent *profileEvent; 2552SN/A 2562SN/A protected: 2572680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2582SN/A 2594776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2604776Sgblack@eecs.umich.edu 2612SN/A public: 262393SN/A 2637764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2647764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2657764Sgblack@eecs.umich.edu 2664776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2674776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2684776Sgblack@eecs.umich.edu 269393SN/A /// Notify the CPU that the indicated context is now active. The 270393SN/A /// delay parameter indicates the number of ticks to wait before 271393SN/A /// executing (typically 0 or 1). 2729180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay) {} 273393SN/A 274393SN/A /// Notify the CPU that the indicated context is now suspended. 2758737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 276393SN/A 277393SN/A /// Notify the CPU that the indicated context is now deallocated. 2788737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 279393SN/A 280393SN/A /// Notify the CPU that the indicated context is now halted. 2818737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2822SN/A 2834000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2844000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2854000Ssaidi@eecs.umich.edu 2864000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2874000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2884000Ssaidi@eecs.umich.edu 2892SN/A public: 2905529Snate@binkert.org typedef BaseCPUParams Params; 2915529Snate@binkert.org const Params *params() const 2925529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2938876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2941191SN/A virtual ~BaseCPU(); 2952SN/A 2961129SN/A virtual void init(); 2971917SN/A virtual void startup(); 2982SN/A virtual void regStats(); 2992SN/A 3006221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 3012103SN/A 3022680Sktlim@umich.edu void registerThreadContexts(); 303180SN/A 3049254SAndreas.Sandberg@arm.com /** 3059254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 3069254SAndreas.Sandberg@arm.com * 3079254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 3089254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 3099254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 3109254SAndreas.Sandberg@arm.com */ 3112798Sktlim@umich.edu virtual void switchOut(); 312180SN/A 3139254SAndreas.Sandberg@arm.com /** 3149254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 3159254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3169254SAndreas.Sandberg@arm.com * 3179254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3189254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3199254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3209254SAndreas.Sandberg@arm.com * CPU. 3219254SAndreas.Sandberg@arm.com * 3229254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3239254SAndreas.Sandberg@arm.com */ 3249254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 325180SN/A 326124SN/A /** 3279446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3289446SAndreas.Sandberg@ARM.com * 3299446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3309446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3319446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3329446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3339446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3349446SAndreas.Sandberg@ARM.com */ 3359446SAndreas.Sandberg@ARM.com void flushTLBs(); 3369446SAndreas.Sandberg@ARM.com 3379446SAndreas.Sandberg@ARM.com /** 3389430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3399430SAndreas.Sandberg@ARM.com * 3409430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3419430SAndreas.Sandberg@ARM.com */ 3429430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3439430SAndreas.Sandberg@ARM.com 3449430SAndreas.Sandberg@ARM.com /** 345124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 346124SN/A * This is a constant for the duration of the simulation. 347124SN/A */ 3486221Snate@binkert.org ThreadID numThreads; 3492SN/A 350124SN/A /** 351124SN/A * Vector of per-thread instruction-based event queues. Used for 352124SN/A * scheduling events based on number of instructions committed by 353124SN/A * a particular thread. 354124SN/A */ 355503SN/A EventQueue **comInstEventQueue; 3562SN/A 357124SN/A /** 358124SN/A * Vector of per-thread load-based event queues. Used for 359124SN/A * scheduling events based on number of loads committed by 360124SN/A *a particular thread. 361124SN/A */ 362124SN/A EventQueue **comLoadEventQueue; 363124SN/A 3642SN/A System *system; 365921SN/A 366921SN/A /** 367921SN/A * Serialize this object to the given output stream. 368921SN/A * @param os The stream to serialize to. 369921SN/A */ 370921SN/A virtual void serialize(std::ostream &os); 371921SN/A 372921SN/A /** 373921SN/A * Reconstruct the state of this object from a checkpoint. 374921SN/A * @param cp The checkpoint use. 375921SN/A * @param section The section name of this object 376921SN/A */ 377921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 378921SN/A 379124SN/A /** 380124SN/A * Return pointer to CPU's branch predictor (NULL if none). 381124SN/A * @return Branch predictor pointer. 382124SN/A */ 3832SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3842SN/A 3858834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 3868834Satgutier@umich.edu 3878834Satgutier@umich.edu virtual Counter totalOps() const = 0; 388707SN/A 3891191SN/A // Function tracing 3901191SN/A private: 3911191SN/A bool functionTracingEnabled; 3921191SN/A std::ostream *functionTraceStream; 3931191SN/A Addr currentFunctionStart; 3941191SN/A Addr currentFunctionEnd; 3951191SN/A Tick functionEntryTick; 3961191SN/A void enableFunctionTrace(); 3971191SN/A void traceFunctionsInternal(Addr pc); 3981191SN/A 3998662SAli.Saidi@ARM.com private: 4008662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 4018662SAli.Saidi@ARM.com 4028662SAli.Saidi@ARM.com public: 4031191SN/A void traceFunctions(Addr pc) 4041191SN/A { 4051191SN/A if (functionTracingEnabled) 4061191SN/A traceFunctionsInternal(pc); 4071191SN/A } 4081191SN/A 4092SN/A static int numSimulatedCPUs() { return cpuList.size(); } 4108834Satgutier@umich.edu static Counter numSimulatedInsts() 411707SN/A { 412707SN/A Counter total = 0; 413707SN/A 414707SN/A int size = cpuList.size(); 415707SN/A for (int i = 0; i < size; ++i) 4168834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 4178834Satgutier@umich.edu 4188834Satgutier@umich.edu return total; 4198834Satgutier@umich.edu } 4208834Satgutier@umich.edu 4218834Satgutier@umich.edu static Counter numSimulatedOps() 4228834Satgutier@umich.edu { 4238834Satgutier@umich.edu Counter total = 0; 4248834Satgutier@umich.edu 4258834Satgutier@umich.edu int size = cpuList.size(); 4268834Satgutier@umich.edu for (int i = 0; i < size; ++i) 4278834Satgutier@umich.edu total += cpuList[i]->totalOps(); 428707SN/A 429707SN/A return total; 430707SN/A } 431707SN/A 432707SN/A public: 433707SN/A // Number of CPU cycles simulated 4345999Snate@binkert.org Stats::Scalar numCycles; 4357914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 4367914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 4372SN/A}; 4382SN/A 4391717SN/A#endif // __CPU_BASE_HH__ 440