base.hh revision 9254
12SN/A/*
28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited
38707Sandreas.hansson@arm.com * All rights reserved
48707Sandreas.hansson@arm.com *
58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98707Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138707Sandreas.hansson@arm.com *
141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California
162SN/A * All rights reserved.
172SN/A *
182SN/A * Redistribution and use in source and binary forms, with or without
192SN/A * modification, are permitted provided that the following conditions are
202SN/A * met: redistributions of source code must retain the above copyright
212SN/A * notice, this list of conditions and the following disclaimer;
222SN/A * redistributions in binary form must reproduce the above copyright
232SN/A * notice, this list of conditions and the following disclaimer in the
242SN/A * documentation and/or other materials provided with the distribution;
252SN/A * neither the name of the copyright holders nor the names of its
262SN/A * contributors may be used to endorse or promote products derived from
272SN/A * this software without specific prior written permission.
282SN/A *
292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665Ssaidi@eecs.umich.edu *
412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
422665Ssaidi@eecs.umich.edu *          Nathan Binkert
437897Shestness@cs.utexas.edu *          Rick Strong
442SN/A */
452SN/A
461717SN/A#ifndef __CPU_BASE_HH__
471717SN/A#define __CPU_BASE_HH__
482SN/A
492SN/A#include <vector>
502SN/A
518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh"
524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh"
535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh"
54707SN/A#include "base/statistics.hh"
556658Snate@binkert.org#include "config/the_isa.hh"
568229Snate@binkert.org#include "mem/mem_object.hh"
5756SN/A#include "sim/eventq.hh"
588779Sgblack@eecs.umich.edu#include "sim/full_system.hh"
594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh"
602SN/A
618901Sandreas.hansson@arm.comstruct BaseCPUParams;
622190SN/Aclass BranchPred;
632315SN/Aclass CheckerCPU;
642680Sktlim@umich.educlass ThreadContext;
652SN/Aclass System;
662SN/A
672356SN/Aclass CPUProgressEvent : public Event
682356SN/A{
692356SN/A  protected:
706144Sksewell@umich.edu    Tick _interval;
712356SN/A    Counter lastNumInst;
722356SN/A    BaseCPU *cpu;
736144Sksewell@umich.edu    bool _repeatEvent;
742356SN/A
752356SN/A  public:
766144Sksewell@umich.edu    CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
772356SN/A
782356SN/A    void process();
792356SN/A
806144Sksewell@umich.edu    void interval(Tick ival) { _interval = ival; }
816144Sksewell@umich.edu    Tick interval() { return _interval; }
826144Sksewell@umich.edu
836144Sksewell@umich.edu    void repeatEvent(bool repeat) { _repeatEvent = repeat; }
846144Sksewell@umich.edu
855336Shines@cs.fsu.edu    virtual const char *description() const;
862356SN/A};
872356SN/A
882856Srdreslin@umich.educlass BaseCPU : public MemObject
892SN/A{
901634SN/A  protected:
919157Sandreas.hansson@arm.com
923814Ssaidi@eecs.umich.edu    // @todo remove me after debugging with legion done
933814Ssaidi@eecs.umich.edu    Tick instCnt;
945712Shsul@eecs.umich.edu    // every cpu has an id, put it in the base cpu
955712Shsul@eecs.umich.edu    // Set at initialization, only time a cpuId might change is during a
965715Shsul@eecs.umich.edu    // takeover (which should be done from within the BaseCPU anyway,
975712Shsul@eecs.umich.edu    // therefore no setCpuId() method is provided
985712Shsul@eecs.umich.edu    int _cpuId;
991634SN/A
1008832SAli.Saidi@ARM.com    /** instruction side request id that must be placed in all requests */
1018832SAli.Saidi@ARM.com    MasterID _instMasterId;
1028832SAli.Saidi@ARM.com
1038832SAli.Saidi@ARM.com    /** data side request id that must be placed in all requests */
1048832SAli.Saidi@ARM.com    MasterID _dataMasterId;
1058832SAli.Saidi@ARM.com
1068707Sandreas.hansson@arm.com    /**
1078707Sandreas.hansson@arm.com     * Define a base class for the CPU ports (instruction and data)
1088707Sandreas.hansson@arm.com     * that is refined in the subclasses. This class handles the
1098707Sandreas.hansson@arm.com     * common cases, i.e. the functional accesses and the status
1108707Sandreas.hansson@arm.com     * changes and address range queries. The default behaviour for
1118707Sandreas.hansson@arm.com     * both atomic and timing access is to panic and the corresponding
1128707Sandreas.hansson@arm.com     * subclasses have to override these methods.
1138707Sandreas.hansson@arm.com     */
1148922Swilliam.wang@arm.com    class CpuPort : public MasterPort
1158707Sandreas.hansson@arm.com    {
1168707Sandreas.hansson@arm.com      public:
1178707Sandreas.hansson@arm.com
1188707Sandreas.hansson@arm.com        /**
1198707Sandreas.hansson@arm.com         * Create a CPU port with a name and a structural owner.
1208707Sandreas.hansson@arm.com         *
1218707Sandreas.hansson@arm.com         * @param _name port name including the owner
1228707Sandreas.hansson@arm.com         * @param _name structural owner of this port
1238707Sandreas.hansson@arm.com         */
1248707Sandreas.hansson@arm.com        CpuPort(const std::string& _name, MemObject* _owner) :
1258922Swilliam.wang@arm.com            MasterPort(_name, _owner)
1268707Sandreas.hansson@arm.com        { }
1278707Sandreas.hansson@arm.com
1288707Sandreas.hansson@arm.com      protected:
1298707Sandreas.hansson@arm.com
1308975Sandreas.hansson@arm.com        virtual bool recvTimingResp(PacketPtr pkt);
1318707Sandreas.hansson@arm.com
1328707Sandreas.hansson@arm.com        virtual void recvRetry();
1338707Sandreas.hansson@arm.com
1348948Sandreas.hansson@arm.com        virtual void recvFunctionalSnoop(PacketPtr pkt);
1358707Sandreas.hansson@arm.com
1368707Sandreas.hansson@arm.com    };
1378707Sandreas.hansson@arm.com
1381634SN/A  public:
1398850Sandreas.hansson@arm.com
1408850Sandreas.hansson@arm.com    /**
1418850Sandreas.hansson@arm.com     * Purely virtual method that returns a reference to the data
1428850Sandreas.hansson@arm.com     * port. All subclasses must implement this method.
1438850Sandreas.hansson@arm.com     *
1448850Sandreas.hansson@arm.com     * @return a reference to the data port
1458850Sandreas.hansson@arm.com     */
1468850Sandreas.hansson@arm.com    virtual CpuPort &getDataPort() = 0;
1478850Sandreas.hansson@arm.com
1488850Sandreas.hansson@arm.com    /**
1498850Sandreas.hansson@arm.com     * Purely virtual method that returns a reference to the instruction
1508850Sandreas.hansson@arm.com     * port. All subclasses must implement this method.
1518850Sandreas.hansson@arm.com     *
1528850Sandreas.hansson@arm.com     * @return a reference to the instruction port
1538850Sandreas.hansson@arm.com     */
1548850Sandreas.hansson@arm.com    virtual CpuPort &getInstPort() = 0;
1558850Sandreas.hansson@arm.com
1565712Shsul@eecs.umich.edu    /** Reads this CPU's ID. */
1575712Shsul@eecs.umich.edu    int cpuId() { return _cpuId; }
1585712Shsul@eecs.umich.edu
1598832SAli.Saidi@ARM.com    /** Reads this CPU's unique data requestor ID */
1608832SAli.Saidi@ARM.com    MasterID dataMasterId() { return _dataMasterId; }
1618832SAli.Saidi@ARM.com    /** Reads this CPU's unique instruction requestor ID */
1628832SAli.Saidi@ARM.com    MasterID instMasterId() { return _instMasterId; }
1638832SAli.Saidi@ARM.com
1648850Sandreas.hansson@arm.com    /**
1658926Sandreas.hansson@arm.com     * Get a master port on this CPU. All CPUs have a data and
1668926Sandreas.hansson@arm.com     * instruction port, and this method uses getDataPort and
1678926Sandreas.hansson@arm.com     * getInstPort of the subclasses to resolve the two ports.
1688850Sandreas.hansson@arm.com     *
1698850Sandreas.hansson@arm.com     * @param if_name the port name
1708850Sandreas.hansson@arm.com     * @param idx ignored index
1718850Sandreas.hansson@arm.com     *
1728922Swilliam.wang@arm.com     * @return a reference to the port with the given name
1738850Sandreas.hansson@arm.com     */
1748926Sandreas.hansson@arm.com    MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
1758850Sandreas.hansson@arm.com
1767914SBrad.Beckmann@amd.com    inline void workItemBegin() { numWorkItemsStarted++; }
1777914SBrad.Beckmann@amd.com    inline void workItemEnd() { numWorkItemsCompleted++; }
1783814Ssaidi@eecs.umich.edu    // @todo remove me after debugging with legion done
1793814Ssaidi@eecs.umich.edu    Tick instCount() { return instCnt; }
1801634SN/A
1815664Sgblack@eecs.umich.edu    TheISA::MicrocodeRom microcodeRom;
1825664Sgblack@eecs.umich.edu
1832SN/A  protected:
1845704Snate@binkert.org    TheISA::Interrupts *interrupts;
1852SN/A
1862SN/A  public:
1875645Sgblack@eecs.umich.edu    TheISA::Interrupts *
1885645Sgblack@eecs.umich.edu    getInterruptController()
1895645Sgblack@eecs.umich.edu    {
1905647Sgblack@eecs.umich.edu        return interrupts;
1915645Sgblack@eecs.umich.edu    }
1925645Sgblack@eecs.umich.edu
1935807Snate@binkert.org    virtual void wakeup() = 0;
1945807Snate@binkert.org
1955807Snate@binkert.org    void
1965807Snate@binkert.org    postInterrupt(int int_num, int index)
1975807Snate@binkert.org    {
1985807Snate@binkert.org        interrupts->post(int_num, index);
1998779Sgblack@eecs.umich.edu        if (FullSystem)
2008779Sgblack@eecs.umich.edu            wakeup();
2015807Snate@binkert.org    }
2025807Snate@binkert.org
2035807Snate@binkert.org    void
2045807Snate@binkert.org    clearInterrupt(int int_num, int index)
2055807Snate@binkert.org    {
2065807Snate@binkert.org        interrupts->clear(int_num, index);
2075807Snate@binkert.org    }
2085807Snate@binkert.org
2095807Snate@binkert.org    void
2105807Snate@binkert.org    clearInterrupts()
2115807Snate@binkert.org    {
2125807Snate@binkert.org        interrupts->clearAll();
2135807Snate@binkert.org    }
2142SN/A
2155704Snate@binkert.org    bool
2165704Snate@binkert.org    checkInterrupts(ThreadContext *tc) const
2175704Snate@binkert.org    {
2188793Sgblack@eecs.umich.edu        return FullSystem && interrupts->checkInterrupts(tc);
2195704Snate@binkert.org    }
2201917SN/A
2211917SN/A    class ProfileEvent : public Event
2221917SN/A    {
2231917SN/A      private:
2241917SN/A        BaseCPU *cpu;
2255536Srstrong@hp.com        Tick interval;
2261917SN/A
2271917SN/A      public:
2285536Srstrong@hp.com        ProfileEvent(BaseCPU *cpu, Tick interval);
2291917SN/A        void process();
2301917SN/A    };
2311917SN/A    ProfileEvent *profileEvent;
2322SN/A
2332SN/A  protected:
2342680Sktlim@umich.edu    std::vector<ThreadContext *> threadContexts;
2352SN/A
2364776Sgblack@eecs.umich.edu    Trace::InstTracer * tracer;
2374776Sgblack@eecs.umich.edu
2382SN/A  public:
239393SN/A
2407764Sgblack@eecs.umich.edu    // Mask to align PCs to MachInst sized boundaries
2417764Sgblack@eecs.umich.edu    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
2427764Sgblack@eecs.umich.edu
2434776Sgblack@eecs.umich.edu    /// Provide access to the tracer pointer
2444776Sgblack@eecs.umich.edu    Trace::InstTracer * getTracer() { return tracer; }
2454776Sgblack@eecs.umich.edu
246393SN/A    /// Notify the CPU that the indicated context is now active.  The
247393SN/A    /// delay parameter indicates the number of ticks to wait before
248393SN/A    /// executing (typically 0 or 1).
2499180Sandreas.hansson@arm.com    virtual void activateContext(ThreadID thread_num, Cycles delay) {}
250393SN/A
251393SN/A    /// Notify the CPU that the indicated context is now suspended.
2528737Skoansin.tan@gmail.com    virtual void suspendContext(ThreadID thread_num) {}
253393SN/A
254393SN/A    /// Notify the CPU that the indicated context is now deallocated.
2558737Skoansin.tan@gmail.com    virtual void deallocateContext(ThreadID thread_num) {}
256393SN/A
257393SN/A    /// Notify the CPU that the indicated context is now halted.
2588737Skoansin.tan@gmail.com    virtual void haltContext(ThreadID thread_num) {}
2592SN/A
2604000Ssaidi@eecs.umich.edu   /// Given a Thread Context pointer return the thread num
2614000Ssaidi@eecs.umich.edu   int findContext(ThreadContext *tc);
2624000Ssaidi@eecs.umich.edu
2634000Ssaidi@eecs.umich.edu   /// Given a thread num get tho thread context for it
2644000Ssaidi@eecs.umich.edu   ThreadContext *getContext(int tn) { return threadContexts[tn]; }
2654000Ssaidi@eecs.umich.edu
2662SN/A  public:
2675529Snate@binkert.org    typedef BaseCPUParams Params;
2685529Snate@binkert.org    const Params *params() const
2695529Snate@binkert.org    { return reinterpret_cast<const Params *>(_params); }
2708876Sandreas.hansson@arm.com    BaseCPU(Params *params, bool is_checker = false);
2711191SN/A    virtual ~BaseCPU();
2722SN/A
2731129SN/A    virtual void init();
2741917SN/A    virtual void startup();
2752SN/A    virtual void regStats();
2762SN/A
2776221Snate@binkert.org    virtual void activateWhenReady(ThreadID tid) {};
2782103SN/A
2792680Sktlim@umich.edu    void registerThreadContexts();
280180SN/A
2819254SAndreas.Sandberg@arm.com    /**
2829254SAndreas.Sandberg@arm.com     * Prepare for another CPU to take over execution.
2839254SAndreas.Sandberg@arm.com     *
2849254SAndreas.Sandberg@arm.com     * When this method exits, all internal state should have been
2859254SAndreas.Sandberg@arm.com     * flushed. After the method returns, the simulator calls
2869254SAndreas.Sandberg@arm.com     * takeOverFrom() on the new CPU with this CPU as its parameter.
2879254SAndreas.Sandberg@arm.com     */
2882798Sktlim@umich.edu    virtual void switchOut();
289180SN/A
2909254SAndreas.Sandberg@arm.com    /**
2919254SAndreas.Sandberg@arm.com     * Load the state of a CPU from the previous CPU object, invoked
2929254SAndreas.Sandberg@arm.com     * on all new CPUs that are about to be switched in.
2939254SAndreas.Sandberg@arm.com     *
2949254SAndreas.Sandberg@arm.com     * A CPU model implementing this method is expected to initialize
2959254SAndreas.Sandberg@arm.com     * its state from the old CPU and connect its memory (unless they
2969254SAndreas.Sandberg@arm.com     * are already connected) to the memories connected to the old
2979254SAndreas.Sandberg@arm.com     * CPU.
2989254SAndreas.Sandberg@arm.com     *
2999254SAndreas.Sandberg@arm.com     * @param cpu CPU to initialize read state from.
3009254SAndreas.Sandberg@arm.com     */
3019254SAndreas.Sandberg@arm.com    virtual void takeOverFrom(BaseCPU *cpu);
302180SN/A
303124SN/A    /**
304124SN/A     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
305124SN/A     * This is a constant for the duration of the simulation.
306124SN/A     */
3076221Snate@binkert.org    ThreadID numThreads;
3082SN/A
309124SN/A    /**
310124SN/A     * Vector of per-thread instruction-based event queues.  Used for
311124SN/A     * scheduling events based on number of instructions committed by
312124SN/A     * a particular thread.
313124SN/A     */
314503SN/A    EventQueue **comInstEventQueue;
3152SN/A
316124SN/A    /**
317124SN/A     * Vector of per-thread load-based event queues.  Used for
318124SN/A     * scheduling events based on number of loads committed by
319124SN/A     *a particular thread.
320124SN/A     */
321124SN/A    EventQueue **comLoadEventQueue;
322124SN/A
3232SN/A    System *system;
324921SN/A
325921SN/A    /**
326921SN/A     * Serialize this object to the given output stream.
327921SN/A     * @param os The stream to serialize to.
328921SN/A     */
329921SN/A    virtual void serialize(std::ostream &os);
330921SN/A
331921SN/A    /**
332921SN/A     * Reconstruct the state of this object from a checkpoint.
333921SN/A     * @param cp The checkpoint use.
334921SN/A     * @param section The section name of this object
335921SN/A     */
336921SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
337921SN/A
338124SN/A    /**
339124SN/A     * Return pointer to CPU's branch predictor (NULL if none).
340124SN/A     * @return Branch predictor pointer.
341124SN/A     */
3422SN/A    virtual BranchPred *getBranchPred() { return NULL; };
3432SN/A
3448834Satgutier@umich.edu    virtual Counter totalInsts() const = 0;
3458834Satgutier@umich.edu
3468834Satgutier@umich.edu    virtual Counter totalOps() const = 0;
347707SN/A
3481191SN/A    // Function tracing
3491191SN/A  private:
3501191SN/A    bool functionTracingEnabled;
3511191SN/A    std::ostream *functionTraceStream;
3521191SN/A    Addr currentFunctionStart;
3531191SN/A    Addr currentFunctionEnd;
3541191SN/A    Tick functionEntryTick;
3551191SN/A    void enableFunctionTrace();
3561191SN/A    void traceFunctionsInternal(Addr pc);
3571191SN/A
3588662SAli.Saidi@ARM.com  private:
3598662SAli.Saidi@ARM.com    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
3608662SAli.Saidi@ARM.com
3618662SAli.Saidi@ARM.com  public:
3621191SN/A    void traceFunctions(Addr pc)
3631191SN/A    {
3641191SN/A        if (functionTracingEnabled)
3651191SN/A            traceFunctionsInternal(pc);
3661191SN/A    }
3671191SN/A
3682SN/A    static int numSimulatedCPUs() { return cpuList.size(); }
3698834Satgutier@umich.edu    static Counter numSimulatedInsts()
370707SN/A    {
371707SN/A        Counter total = 0;
372707SN/A
373707SN/A        int size = cpuList.size();
374707SN/A        for (int i = 0; i < size; ++i)
3758834Satgutier@umich.edu            total += cpuList[i]->totalInsts();
3768834Satgutier@umich.edu
3778834Satgutier@umich.edu        return total;
3788834Satgutier@umich.edu    }
3798834Satgutier@umich.edu
3808834Satgutier@umich.edu    static Counter numSimulatedOps()
3818834Satgutier@umich.edu    {
3828834Satgutier@umich.edu        Counter total = 0;
3838834Satgutier@umich.edu
3848834Satgutier@umich.edu        int size = cpuList.size();
3858834Satgutier@umich.edu        for (int i = 0; i < size; ++i)
3868834Satgutier@umich.edu            total += cpuList[i]->totalOps();
387707SN/A
388707SN/A        return total;
389707SN/A    }
390707SN/A
391707SN/A  public:
392707SN/A    // Number of CPU cycles simulated
3935999Snate@binkert.org    Stats::Scalar numCycles;
3947914SBrad.Beckmann@amd.com    Stats::Scalar numWorkItemsStarted;
3957914SBrad.Beckmann@amd.com    Stats::Scalar numWorkItemsCompleted;
3962SN/A};
3972SN/A
3981717SN/A#endif // __CPU_BASE_HH__
399