base.hh revision 8975
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 54707SN/A#include "base/statistics.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 602SN/A 618901Sandreas.hansson@arm.comstruct BaseCPUParams; 622190SN/Aclass BranchPred; 632315SN/Aclass CheckerCPU; 642680Sktlim@umich.educlass ThreadContext; 652SN/Aclass System; 662SN/A 674182Sgblack@eecs.umich.edunamespace TheISA 684182Sgblack@eecs.umich.edu{ 694182Sgblack@eecs.umich.edu class Predecoder; 704182Sgblack@eecs.umich.edu} 714182Sgblack@eecs.umich.edu 722356SN/Aclass CPUProgressEvent : public Event 732356SN/A{ 742356SN/A protected: 756144Sksewell@umich.edu Tick _interval; 762356SN/A Counter lastNumInst; 772356SN/A BaseCPU *cpu; 786144Sksewell@umich.edu bool _repeatEvent; 792356SN/A 802356SN/A public: 816144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 822356SN/A 832356SN/A void process(); 842356SN/A 856144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 866144Sksewell@umich.edu Tick interval() { return _interval; } 876144Sksewell@umich.edu 886144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 896144Sksewell@umich.edu 905336Shines@cs.fsu.edu virtual const char *description() const; 912356SN/A}; 922356SN/A 932856Srdreslin@umich.educlass BaseCPU : public MemObject 942SN/A{ 951634SN/A protected: 961634SN/A // CPU's clock period in terms of the number of ticks of curTime. 971695SN/A Tick clock; 983814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 993814Ssaidi@eecs.umich.edu Tick instCnt; 1005712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1015712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1025715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1035712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1045712Shsul@eecs.umich.edu int _cpuId; 1051634SN/A 1068832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1078832SAli.Saidi@ARM.com MasterID _instMasterId; 1088832SAli.Saidi@ARM.com 1098832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1108832SAli.Saidi@ARM.com MasterID _dataMasterId; 1118832SAli.Saidi@ARM.com 1128707Sandreas.hansson@arm.com /** 1138707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1148707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1158707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1168707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1178707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1188707Sandreas.hansson@arm.com * subclasses have to override these methods. 1198707Sandreas.hansson@arm.com */ 1208922Swilliam.wang@arm.com class CpuPort : public MasterPort 1218707Sandreas.hansson@arm.com { 1228707Sandreas.hansson@arm.com public: 1238707Sandreas.hansson@arm.com 1248707Sandreas.hansson@arm.com /** 1258707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1268707Sandreas.hansson@arm.com * 1278707Sandreas.hansson@arm.com * @param _name port name including the owner 1288707Sandreas.hansson@arm.com * @param _name structural owner of this port 1298707Sandreas.hansson@arm.com */ 1308707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1318922Swilliam.wang@arm.com MasterPort(_name, _owner) 1328707Sandreas.hansson@arm.com { } 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com protected: 1358707Sandreas.hansson@arm.com 1368975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1378707Sandreas.hansson@arm.com 1388707Sandreas.hansson@arm.com virtual void recvRetry(); 1398707Sandreas.hansson@arm.com 1408948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1418707Sandreas.hansson@arm.com 1428707Sandreas.hansson@arm.com }; 1438707Sandreas.hansson@arm.com 1441634SN/A public: 1458850Sandreas.hansson@arm.com 1468850Sandreas.hansson@arm.com /** 1478850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1488850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1498850Sandreas.hansson@arm.com * 1508850Sandreas.hansson@arm.com * @return a reference to the data port 1518850Sandreas.hansson@arm.com */ 1528850Sandreas.hansson@arm.com virtual CpuPort &getDataPort() = 0; 1538850Sandreas.hansson@arm.com 1548850Sandreas.hansson@arm.com /** 1558850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1568850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1578850Sandreas.hansson@arm.com * 1588850Sandreas.hansson@arm.com * @return a reference to the instruction port 1598850Sandreas.hansson@arm.com */ 1608850Sandreas.hansson@arm.com virtual CpuPort &getInstPort() = 0; 1618850Sandreas.hansson@arm.com 1625712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1635712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1645712Shsul@eecs.umich.edu 1658832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1668832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1678832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1688832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1698832SAli.Saidi@ARM.com 1708850Sandreas.hansson@arm.com /** 1718926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1728926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1738926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1748850Sandreas.hansson@arm.com * 1758850Sandreas.hansson@arm.com * @param if_name the port name 1768850Sandreas.hansson@arm.com * @param idx ignored index 1778850Sandreas.hansson@arm.com * 1788922Swilliam.wang@arm.com * @return a reference to the port with the given name 1798850Sandreas.hansson@arm.com */ 1808926Sandreas.hansson@arm.com MasterPort &getMasterPort(const std::string &if_name, int idx = -1); 1818850Sandreas.hansson@arm.com 1822359SN/A// Tick currentTick; 1837064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1845100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1857823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1865099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1877914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1887914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1893814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1903814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1911634SN/A 1923495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1933495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1947823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1953495Sktlim@umich.edu */ 1963495Sktlim@umich.edu Tick nextCycle(); 1973495Sktlim@umich.edu 1983495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1993495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 2007823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 2013495Sktlim@umich.edu * current cycle. 2023495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 2033495Sktlim@umich.edu */ 2043495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 2053495Sktlim@umich.edu 2065664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2075664Sgblack@eecs.umich.edu 2082SN/A protected: 2095704Snate@binkert.org TheISA::Interrupts *interrupts; 2102SN/A 2112SN/A public: 2125645Sgblack@eecs.umich.edu TheISA::Interrupts * 2135645Sgblack@eecs.umich.edu getInterruptController() 2145645Sgblack@eecs.umich.edu { 2155647Sgblack@eecs.umich.edu return interrupts; 2165645Sgblack@eecs.umich.edu } 2175645Sgblack@eecs.umich.edu 2185807Snate@binkert.org virtual void wakeup() = 0; 2195807Snate@binkert.org 2205807Snate@binkert.org void 2215807Snate@binkert.org postInterrupt(int int_num, int index) 2225807Snate@binkert.org { 2235807Snate@binkert.org interrupts->post(int_num, index); 2248779Sgblack@eecs.umich.edu if (FullSystem) 2258779Sgblack@eecs.umich.edu wakeup(); 2265807Snate@binkert.org } 2275807Snate@binkert.org 2285807Snate@binkert.org void 2295807Snate@binkert.org clearInterrupt(int int_num, int index) 2305807Snate@binkert.org { 2315807Snate@binkert.org interrupts->clear(int_num, index); 2325807Snate@binkert.org } 2335807Snate@binkert.org 2345807Snate@binkert.org void 2355807Snate@binkert.org clearInterrupts() 2365807Snate@binkert.org { 2375807Snate@binkert.org interrupts->clearAll(); 2385807Snate@binkert.org } 2392SN/A 2405704Snate@binkert.org bool 2415704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2425704Snate@binkert.org { 2438793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2445704Snate@binkert.org } 2451917SN/A 2461917SN/A class ProfileEvent : public Event 2471917SN/A { 2481917SN/A private: 2491917SN/A BaseCPU *cpu; 2505536Srstrong@hp.com Tick interval; 2511917SN/A 2521917SN/A public: 2535536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2541917SN/A void process(); 2551917SN/A }; 2561917SN/A ProfileEvent *profileEvent; 2572SN/A 2582SN/A protected: 2592680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2604182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 2612SN/A 2624776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2634776Sgblack@eecs.umich.edu 2642SN/A public: 265393SN/A 2667764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2677764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2687764Sgblack@eecs.umich.edu 2694776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2704776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2714776Sgblack@eecs.umich.edu 272393SN/A /// Notify the CPU that the indicated context is now active. The 273393SN/A /// delay parameter indicates the number of ticks to wait before 274393SN/A /// executing (typically 0 or 1). 2758737Skoansin.tan@gmail.com virtual void activateContext(ThreadID thread_num, int delay) {} 276393SN/A 277393SN/A /// Notify the CPU that the indicated context is now suspended. 2788737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 279393SN/A 280393SN/A /// Notify the CPU that the indicated context is now deallocated. 2818737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 282393SN/A 283393SN/A /// Notify the CPU that the indicated context is now halted. 2848737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2852SN/A 2864000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2874000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2884000Ssaidi@eecs.umich.edu 2894000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2904000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2914000Ssaidi@eecs.umich.edu 2922SN/A public: 2935529Snate@binkert.org typedef BaseCPUParams Params; 2945529Snate@binkert.org const Params *params() const 2955529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2968876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2971191SN/A virtual ~BaseCPU(); 2982SN/A 2991129SN/A virtual void init(); 3001917SN/A virtual void startup(); 3012SN/A virtual void regStats(); 3022SN/A 3036221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 3042103SN/A 3052680Sktlim@umich.edu void registerThreadContexts(); 306180SN/A 3071492SN/A /// Prepare for another CPU to take over execution. When it is 3081492SN/A /// is ready (drained pipe) it signals the sampler. 3092798Sktlim@umich.edu virtual void switchOut(); 310180SN/A 311180SN/A /// Take over execution from the given CPU. Used for warm-up and 312180SN/A /// sampling. 3138737Skoansin.tan@gmail.com virtual void takeOverFrom(BaseCPU *); 314180SN/A 315124SN/A /** 316124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 317124SN/A * This is a constant for the duration of the simulation. 318124SN/A */ 3196221Snate@binkert.org ThreadID numThreads; 3202SN/A 321124SN/A /** 322124SN/A * Vector of per-thread instruction-based event queues. Used for 323124SN/A * scheduling events based on number of instructions committed by 324124SN/A * a particular thread. 325124SN/A */ 326503SN/A EventQueue **comInstEventQueue; 3272SN/A 328124SN/A /** 329124SN/A * Vector of per-thread load-based event queues. Used for 330124SN/A * scheduling events based on number of loads committed by 331124SN/A *a particular thread. 332124SN/A */ 333124SN/A EventQueue **comLoadEventQueue; 334124SN/A 3352SN/A System *system; 336921SN/A 3373661Srdreslin@umich.edu Tick phase; 3383661Srdreslin@umich.edu 339921SN/A /** 340921SN/A * Serialize this object to the given output stream. 341921SN/A * @param os The stream to serialize to. 342921SN/A */ 343921SN/A virtual void serialize(std::ostream &os); 344921SN/A 345921SN/A /** 346921SN/A * Reconstruct the state of this object from a checkpoint. 347921SN/A * @param cp The checkpoint use. 348921SN/A * @param section The section name of this object 349921SN/A */ 350921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 351921SN/A 352124SN/A /** 353124SN/A * Return pointer to CPU's branch predictor (NULL if none). 354124SN/A * @return Branch predictor pointer. 355124SN/A */ 3562SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3572SN/A 3588834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 3598834Satgutier@umich.edu 3608834Satgutier@umich.edu virtual Counter totalOps() const = 0; 361707SN/A 3621191SN/A // Function tracing 3631191SN/A private: 3641191SN/A bool functionTracingEnabled; 3651191SN/A std::ostream *functionTraceStream; 3661191SN/A Addr currentFunctionStart; 3671191SN/A Addr currentFunctionEnd; 3681191SN/A Tick functionEntryTick; 3691191SN/A void enableFunctionTrace(); 3701191SN/A void traceFunctionsInternal(Addr pc); 3711191SN/A 3728662SAli.Saidi@ARM.com private: 3738662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3748662SAli.Saidi@ARM.com 3758662SAli.Saidi@ARM.com public: 3761191SN/A void traceFunctions(Addr pc) 3771191SN/A { 3781191SN/A if (functionTracingEnabled) 3791191SN/A traceFunctionsInternal(pc); 3801191SN/A } 3811191SN/A 3822SN/A static int numSimulatedCPUs() { return cpuList.size(); } 3838834Satgutier@umich.edu static Counter numSimulatedInsts() 384707SN/A { 385707SN/A Counter total = 0; 386707SN/A 387707SN/A int size = cpuList.size(); 388707SN/A for (int i = 0; i < size; ++i) 3898834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 3908834Satgutier@umich.edu 3918834Satgutier@umich.edu return total; 3928834Satgutier@umich.edu } 3938834Satgutier@umich.edu 3948834Satgutier@umich.edu static Counter numSimulatedOps() 3958834Satgutier@umich.edu { 3968834Satgutier@umich.edu Counter total = 0; 3978834Satgutier@umich.edu 3988834Satgutier@umich.edu int size = cpuList.size(); 3998834Satgutier@umich.edu for (int i = 0; i < size; ++i) 4008834Satgutier@umich.edu total += cpuList[i]->totalOps(); 401707SN/A 402707SN/A return total; 403707SN/A } 404707SN/A 405707SN/A public: 406707SN/A // Number of CPU cycles simulated 4075999Snate@binkert.org Stats::Scalar numCycles; 4087914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 4097914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 4102SN/A}; 4112SN/A 4121717SN/A#endif // __CPU_BASE_HH__ 413