base.hh revision 8901
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 54707SN/A#include "base/statistics.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 602SN/A 618901Sandreas.hansson@arm.comstruct BaseCPUParams; 622190SN/Aclass BranchPred; 632315SN/Aclass CheckerCPU; 642680Sktlim@umich.educlass ThreadContext; 652SN/Aclass System; 662SN/A 674182Sgblack@eecs.umich.edunamespace TheISA 684182Sgblack@eecs.umich.edu{ 694182Sgblack@eecs.umich.edu class Predecoder; 704182Sgblack@eecs.umich.edu} 714182Sgblack@eecs.umich.edu 722356SN/Aclass CPUProgressEvent : public Event 732356SN/A{ 742356SN/A protected: 756144Sksewell@umich.edu Tick _interval; 762356SN/A Counter lastNumInst; 772356SN/A BaseCPU *cpu; 786144Sksewell@umich.edu bool _repeatEvent; 792356SN/A 802356SN/A public: 816144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 822356SN/A 832356SN/A void process(); 842356SN/A 856144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 866144Sksewell@umich.edu Tick interval() { return _interval; } 876144Sksewell@umich.edu 886144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 896144Sksewell@umich.edu 905336Shines@cs.fsu.edu virtual const char *description() const; 912356SN/A}; 922356SN/A 932856Srdreslin@umich.educlass BaseCPU : public MemObject 942SN/A{ 951634SN/A protected: 961634SN/A // CPU's clock period in terms of the number of ticks of curTime. 971695SN/A Tick clock; 983814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 993814Ssaidi@eecs.umich.edu Tick instCnt; 1005712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1015712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1025715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1035712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1045712Shsul@eecs.umich.edu int _cpuId; 1051634SN/A 1068832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1078832SAli.Saidi@ARM.com MasterID _instMasterId; 1088832SAli.Saidi@ARM.com 1098832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1108832SAli.Saidi@ARM.com MasterID _dataMasterId; 1118832SAli.Saidi@ARM.com 1128707Sandreas.hansson@arm.com /** 1138707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1148707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1158707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1168707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1178707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1188707Sandreas.hansson@arm.com * subclasses have to override these methods. 1198707Sandreas.hansson@arm.com */ 1208707Sandreas.hansson@arm.com class CpuPort : public Port 1218707Sandreas.hansson@arm.com { 1228707Sandreas.hansson@arm.com public: 1238707Sandreas.hansson@arm.com 1248707Sandreas.hansson@arm.com /** 1258707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1268707Sandreas.hansson@arm.com * 1278707Sandreas.hansson@arm.com * @param _name port name including the owner 1288707Sandreas.hansson@arm.com * @param _name structural owner of this port 1298707Sandreas.hansson@arm.com */ 1308707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1318711Sandreas.hansson@arm.com Port(_name, _owner) 1328707Sandreas.hansson@arm.com { } 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com protected: 1358707Sandreas.hansson@arm.com 1368707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1378707Sandreas.hansson@arm.com 1388707Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 1398707Sandreas.hansson@arm.com 1408707Sandreas.hansson@arm.com virtual void recvRetry(); 1418707Sandreas.hansson@arm.com 1428707Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 1438707Sandreas.hansson@arm.com 1448711Sandreas.hansson@arm.com void recvRangeChange(); 1458707Sandreas.hansson@arm.com 1468707Sandreas.hansson@arm.com }; 1478707Sandreas.hansson@arm.com 1481634SN/A public: 1498850Sandreas.hansson@arm.com 1508850Sandreas.hansson@arm.com /** 1518850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1528850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1538850Sandreas.hansson@arm.com * 1548850Sandreas.hansson@arm.com * @return a reference to the data port 1558850Sandreas.hansson@arm.com */ 1568850Sandreas.hansson@arm.com virtual CpuPort &getDataPort() = 0; 1578850Sandreas.hansson@arm.com 1588850Sandreas.hansson@arm.com /** 1598850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1608850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1618850Sandreas.hansson@arm.com * 1628850Sandreas.hansson@arm.com * @return a reference to the instruction port 1638850Sandreas.hansson@arm.com */ 1648850Sandreas.hansson@arm.com virtual CpuPort &getInstPort() = 0; 1658850Sandreas.hansson@arm.com 1665712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1675712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1685712Shsul@eecs.umich.edu 1698832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1708832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1718832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1728832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1738832SAli.Saidi@ARM.com 1748850Sandreas.hansson@arm.com /** 1758850Sandreas.hansson@arm.com * Get a port on this MemObject. This method is virtual to allow 1768850Sandreas.hansson@arm.com * the subclasses of the BaseCPU to override it. All CPUs have a 1778850Sandreas.hansson@arm.com * data and instruction port, but the Atomic CPU (in its current 1788850Sandreas.hansson@arm.com * form) adds a port directly connected to the memory and has to 1798850Sandreas.hansson@arm.com * override getPort. 1808850Sandreas.hansson@arm.com * 1818850Sandreas.hansson@arm.com * This method uses getDataPort and getInstPort to resolve the two 1828850Sandreas.hansson@arm.com * ports. 1838850Sandreas.hansson@arm.com * 1848850Sandreas.hansson@arm.com * @param if_name the port name 1858850Sandreas.hansson@arm.com * @param idx ignored index 1868850Sandreas.hansson@arm.com * 1878850Sandreas.hansson@arm.com * @return a pointer to the port with the given name 1888850Sandreas.hansson@arm.com */ 1898850Sandreas.hansson@arm.com virtual Port *getPort(const std::string &if_name, int idx = -1); 1908850Sandreas.hansson@arm.com 1912359SN/A// Tick currentTick; 1927064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1935100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1947823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1955099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1967914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1977914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1983814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1993814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 2001634SN/A 2013495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 2023495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 2037823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 2043495Sktlim@umich.edu */ 2053495Sktlim@umich.edu Tick nextCycle(); 2063495Sktlim@umich.edu 2073495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 2083495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 2097823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 2103495Sktlim@umich.edu * current cycle. 2113495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 2123495Sktlim@umich.edu */ 2133495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 2143495Sktlim@umich.edu 2155664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2165664Sgblack@eecs.umich.edu 2172SN/A protected: 2185704Snate@binkert.org TheISA::Interrupts *interrupts; 2192SN/A 2202SN/A public: 2215645Sgblack@eecs.umich.edu TheISA::Interrupts * 2225645Sgblack@eecs.umich.edu getInterruptController() 2235645Sgblack@eecs.umich.edu { 2245647Sgblack@eecs.umich.edu return interrupts; 2255645Sgblack@eecs.umich.edu } 2265645Sgblack@eecs.umich.edu 2275807Snate@binkert.org virtual void wakeup() = 0; 2285807Snate@binkert.org 2295807Snate@binkert.org void 2305807Snate@binkert.org postInterrupt(int int_num, int index) 2315807Snate@binkert.org { 2325807Snate@binkert.org interrupts->post(int_num, index); 2338779Sgblack@eecs.umich.edu if (FullSystem) 2348779Sgblack@eecs.umich.edu wakeup(); 2355807Snate@binkert.org } 2365807Snate@binkert.org 2375807Snate@binkert.org void 2385807Snate@binkert.org clearInterrupt(int int_num, int index) 2395807Snate@binkert.org { 2405807Snate@binkert.org interrupts->clear(int_num, index); 2415807Snate@binkert.org } 2425807Snate@binkert.org 2435807Snate@binkert.org void 2445807Snate@binkert.org clearInterrupts() 2455807Snate@binkert.org { 2465807Snate@binkert.org interrupts->clearAll(); 2475807Snate@binkert.org } 2482SN/A 2495704Snate@binkert.org bool 2505704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2515704Snate@binkert.org { 2528793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2535704Snate@binkert.org } 2541917SN/A 2551917SN/A class ProfileEvent : public Event 2561917SN/A { 2571917SN/A private: 2581917SN/A BaseCPU *cpu; 2595536Srstrong@hp.com Tick interval; 2601917SN/A 2611917SN/A public: 2625536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2631917SN/A void process(); 2641917SN/A }; 2651917SN/A ProfileEvent *profileEvent; 2662SN/A 2672SN/A protected: 2682680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2694182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 2702SN/A 2714776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2724776Sgblack@eecs.umich.edu 2732SN/A public: 274393SN/A 2757764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2767764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2777764Sgblack@eecs.umich.edu 2784776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2794776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2804776Sgblack@eecs.umich.edu 281393SN/A /// Notify the CPU that the indicated context is now active. The 282393SN/A /// delay parameter indicates the number of ticks to wait before 283393SN/A /// executing (typically 0 or 1). 2848737Skoansin.tan@gmail.com virtual void activateContext(ThreadID thread_num, int delay) {} 285393SN/A 286393SN/A /// Notify the CPU that the indicated context is now suspended. 2878737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 288393SN/A 289393SN/A /// Notify the CPU that the indicated context is now deallocated. 2908737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 291393SN/A 292393SN/A /// Notify the CPU that the indicated context is now halted. 2938737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2942SN/A 2954000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2964000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2974000Ssaidi@eecs.umich.edu 2984000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2994000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 3004000Ssaidi@eecs.umich.edu 3012SN/A public: 3025529Snate@binkert.org typedef BaseCPUParams Params; 3035529Snate@binkert.org const Params *params() const 3045529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 3058876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 3061191SN/A virtual ~BaseCPU(); 3072SN/A 3081129SN/A virtual void init(); 3091917SN/A virtual void startup(); 3102SN/A virtual void regStats(); 3112SN/A 3126221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 3132103SN/A 3142680Sktlim@umich.edu void registerThreadContexts(); 315180SN/A 3161492SN/A /// Prepare for another CPU to take over execution. When it is 3171492SN/A /// is ready (drained pipe) it signals the sampler. 3182798Sktlim@umich.edu virtual void switchOut(); 319180SN/A 320180SN/A /// Take over execution from the given CPU. Used for warm-up and 321180SN/A /// sampling. 3228737Skoansin.tan@gmail.com virtual void takeOverFrom(BaseCPU *); 323180SN/A 324124SN/A /** 325124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 326124SN/A * This is a constant for the duration of the simulation. 327124SN/A */ 3286221Snate@binkert.org ThreadID numThreads; 3292SN/A 330124SN/A /** 331124SN/A * Vector of per-thread instruction-based event queues. Used for 332124SN/A * scheduling events based on number of instructions committed by 333124SN/A * a particular thread. 334124SN/A */ 335503SN/A EventQueue **comInstEventQueue; 3362SN/A 337124SN/A /** 338124SN/A * Vector of per-thread load-based event queues. Used for 339124SN/A * scheduling events based on number of loads committed by 340124SN/A *a particular thread. 341124SN/A */ 342124SN/A EventQueue **comLoadEventQueue; 343124SN/A 3442SN/A System *system; 345921SN/A 3463661Srdreslin@umich.edu Tick phase; 3473661Srdreslin@umich.edu 348921SN/A /** 349921SN/A * Serialize this object to the given output stream. 350921SN/A * @param os The stream to serialize to. 351921SN/A */ 352921SN/A virtual void serialize(std::ostream &os); 353921SN/A 354921SN/A /** 355921SN/A * Reconstruct the state of this object from a checkpoint. 356921SN/A * @param cp The checkpoint use. 357921SN/A * @param section The section name of this object 358921SN/A */ 359921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 360921SN/A 361124SN/A /** 362124SN/A * Return pointer to CPU's branch predictor (NULL if none). 363124SN/A * @return Branch predictor pointer. 364124SN/A */ 3652SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3662SN/A 3678834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 3688834Satgutier@umich.edu 3698834Satgutier@umich.edu virtual Counter totalOps() const = 0; 370707SN/A 3711191SN/A // Function tracing 3721191SN/A private: 3731191SN/A bool functionTracingEnabled; 3741191SN/A std::ostream *functionTraceStream; 3751191SN/A Addr currentFunctionStart; 3761191SN/A Addr currentFunctionEnd; 3771191SN/A Tick functionEntryTick; 3781191SN/A void enableFunctionTrace(); 3791191SN/A void traceFunctionsInternal(Addr pc); 3801191SN/A 3818662SAli.Saidi@ARM.com private: 3828662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3838662SAli.Saidi@ARM.com 3848662SAli.Saidi@ARM.com public: 3851191SN/A void traceFunctions(Addr pc) 3861191SN/A { 3871191SN/A if (functionTracingEnabled) 3881191SN/A traceFunctionsInternal(pc); 3891191SN/A } 3901191SN/A 3912SN/A static int numSimulatedCPUs() { return cpuList.size(); } 3928834Satgutier@umich.edu static Counter numSimulatedInsts() 393707SN/A { 394707SN/A Counter total = 0; 395707SN/A 396707SN/A int size = cpuList.size(); 397707SN/A for (int i = 0; i < size; ++i) 3988834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 3998834Satgutier@umich.edu 4008834Satgutier@umich.edu return total; 4018834Satgutier@umich.edu } 4028834Satgutier@umich.edu 4038834Satgutier@umich.edu static Counter numSimulatedOps() 4048834Satgutier@umich.edu { 4058834Satgutier@umich.edu Counter total = 0; 4068834Satgutier@umich.edu 4078834Satgutier@umich.edu int size = cpuList.size(); 4088834Satgutier@umich.edu for (int i = 0; i < size; ++i) 4098834Satgutier@umich.edu total += cpuList[i]->totalOps(); 410707SN/A 411707SN/A return total; 412707SN/A } 413707SN/A 414707SN/A public: 415707SN/A // Number of CPU cycles simulated 4165999Snate@binkert.org Stats::Scalar numCycles; 4177914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 4187914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 4192SN/A}; 4202SN/A 4211717SN/A#endif // __CPU_BASE_HH__ 422