base.hh revision 8834
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 518745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 524182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 535664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 54707SN/A#include "base/statistics.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 594776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 602SN/A 618711Sandreas.hansson@arm.comclass BaseCPUParams; 622190SN/Aclass BranchPred; 632315SN/Aclass CheckerCPU; 642680Sktlim@umich.educlass ThreadContext; 652SN/Aclass System; 662856Srdreslin@umich.educlass Port; 672SN/A 684182Sgblack@eecs.umich.edunamespace TheISA 694182Sgblack@eecs.umich.edu{ 704182Sgblack@eecs.umich.edu class Predecoder; 714182Sgblack@eecs.umich.edu} 724182Sgblack@eecs.umich.edu 732356SN/Aclass CPUProgressEvent : public Event 742356SN/A{ 752356SN/A protected: 766144Sksewell@umich.edu Tick _interval; 772356SN/A Counter lastNumInst; 782356SN/A BaseCPU *cpu; 796144Sksewell@umich.edu bool _repeatEvent; 802356SN/A 812356SN/A public: 826144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 832356SN/A 842356SN/A void process(); 852356SN/A 866144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 876144Sksewell@umich.edu Tick interval() { return _interval; } 886144Sksewell@umich.edu 896144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 906144Sksewell@umich.edu 915336Shines@cs.fsu.edu virtual const char *description() const; 922356SN/A}; 932356SN/A 942856Srdreslin@umich.educlass BaseCPU : public MemObject 952SN/A{ 961634SN/A protected: 971634SN/A // CPU's clock period in terms of the number of ticks of curTime. 981695SN/A Tick clock; 993814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1003814Ssaidi@eecs.umich.edu Tick instCnt; 1015712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1025712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1035715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1045712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1055712Shsul@eecs.umich.edu int _cpuId; 1061634SN/A 1078832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1088832SAli.Saidi@ARM.com MasterID _instMasterId; 1098832SAli.Saidi@ARM.com 1108832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1118832SAli.Saidi@ARM.com MasterID _dataMasterId; 1128832SAli.Saidi@ARM.com 1138707Sandreas.hansson@arm.com /** 1148707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1158707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1168707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1178707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1188707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1198707Sandreas.hansson@arm.com * subclasses have to override these methods. 1208707Sandreas.hansson@arm.com */ 1218707Sandreas.hansson@arm.com class CpuPort : public Port 1228707Sandreas.hansson@arm.com { 1238707Sandreas.hansson@arm.com public: 1248707Sandreas.hansson@arm.com 1258707Sandreas.hansson@arm.com /** 1268707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1278707Sandreas.hansson@arm.com * 1288707Sandreas.hansson@arm.com * @param _name port name including the owner 1298707Sandreas.hansson@arm.com * @param _name structural owner of this port 1308707Sandreas.hansson@arm.com */ 1318707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1328711Sandreas.hansson@arm.com Port(_name, _owner) 1338707Sandreas.hansson@arm.com { } 1348707Sandreas.hansson@arm.com 1358707Sandreas.hansson@arm.com protected: 1368707Sandreas.hansson@arm.com 1378707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1388707Sandreas.hansson@arm.com 1398707Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 1408707Sandreas.hansson@arm.com 1418707Sandreas.hansson@arm.com virtual void recvRetry(); 1428707Sandreas.hansson@arm.com 1438707Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 1448707Sandreas.hansson@arm.com 1458711Sandreas.hansson@arm.com void recvRangeChange(); 1468707Sandreas.hansson@arm.com 1478707Sandreas.hansson@arm.com }; 1488707Sandreas.hansson@arm.com 1491634SN/A public: 1505712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1515712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1525712Shsul@eecs.umich.edu 1538832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1548832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1558832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1568832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1578832SAli.Saidi@ARM.com 1582359SN/A// Tick currentTick; 1597064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1605100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1617823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1625099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1637914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1647914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1653814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1663814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1671634SN/A 1683495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1693495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1707823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1713495Sktlim@umich.edu */ 1723495Sktlim@umich.edu Tick nextCycle(); 1733495Sktlim@umich.edu 1743495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1753495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1767823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1773495Sktlim@umich.edu * current cycle. 1783495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1793495Sktlim@umich.edu */ 1803495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1813495Sktlim@umich.edu 1825664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1835664Sgblack@eecs.umich.edu 1842SN/A protected: 1855704Snate@binkert.org TheISA::Interrupts *interrupts; 1862SN/A 1872SN/A public: 1885645Sgblack@eecs.umich.edu TheISA::Interrupts * 1895645Sgblack@eecs.umich.edu getInterruptController() 1905645Sgblack@eecs.umich.edu { 1915647Sgblack@eecs.umich.edu return interrupts; 1925645Sgblack@eecs.umich.edu } 1935645Sgblack@eecs.umich.edu 1945807Snate@binkert.org virtual void wakeup() = 0; 1955807Snate@binkert.org 1965807Snate@binkert.org void 1975807Snate@binkert.org postInterrupt(int int_num, int index) 1985807Snate@binkert.org { 1995807Snate@binkert.org interrupts->post(int_num, index); 2008779Sgblack@eecs.umich.edu if (FullSystem) 2018779Sgblack@eecs.umich.edu wakeup(); 2025807Snate@binkert.org } 2035807Snate@binkert.org 2045807Snate@binkert.org void 2055807Snate@binkert.org clearInterrupt(int int_num, int index) 2065807Snate@binkert.org { 2075807Snate@binkert.org interrupts->clear(int_num, index); 2085807Snate@binkert.org } 2095807Snate@binkert.org 2105807Snate@binkert.org void 2115807Snate@binkert.org clearInterrupts() 2125807Snate@binkert.org { 2135807Snate@binkert.org interrupts->clearAll(); 2145807Snate@binkert.org } 2152SN/A 2165704Snate@binkert.org bool 2175704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2185704Snate@binkert.org { 2198793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2205704Snate@binkert.org } 2211917SN/A 2221917SN/A class ProfileEvent : public Event 2231917SN/A { 2241917SN/A private: 2251917SN/A BaseCPU *cpu; 2265536Srstrong@hp.com Tick interval; 2271917SN/A 2281917SN/A public: 2295536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2301917SN/A void process(); 2311917SN/A }; 2321917SN/A ProfileEvent *profileEvent; 2332SN/A 2342SN/A protected: 2352680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2364182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 2372SN/A 2384776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2394776Sgblack@eecs.umich.edu 2402SN/A public: 241393SN/A 2427764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2437764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2447764Sgblack@eecs.umich.edu 2454776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2464776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2474776Sgblack@eecs.umich.edu 248393SN/A /// Notify the CPU that the indicated context is now active. The 249393SN/A /// delay parameter indicates the number of ticks to wait before 250393SN/A /// executing (typically 0 or 1). 2518737Skoansin.tan@gmail.com virtual void activateContext(ThreadID thread_num, int delay) {} 252393SN/A 253393SN/A /// Notify the CPU that the indicated context is now suspended. 2548737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 255393SN/A 256393SN/A /// Notify the CPU that the indicated context is now deallocated. 2578737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 258393SN/A 259393SN/A /// Notify the CPU that the indicated context is now halted. 2608737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2612SN/A 2624000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2634000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2644000Ssaidi@eecs.umich.edu 2654000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2664000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2674000Ssaidi@eecs.umich.edu 2682SN/A public: 2695529Snate@binkert.org typedef BaseCPUParams Params; 2705529Snate@binkert.org const Params *params() const 2715529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2721400SN/A BaseCPU(Params *params); 2731191SN/A virtual ~BaseCPU(); 2742SN/A 2751129SN/A virtual void init(); 2761917SN/A virtual void startup(); 2772SN/A virtual void regStats(); 2782SN/A 2796221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2802103SN/A 2812680Sktlim@umich.edu void registerThreadContexts(); 282180SN/A 2831492SN/A /// Prepare for another CPU to take over execution. When it is 2841492SN/A /// is ready (drained pipe) it signals the sampler. 2852798Sktlim@umich.edu virtual void switchOut(); 286180SN/A 287180SN/A /// Take over execution from the given CPU. Used for warm-up and 288180SN/A /// sampling. 2898737Skoansin.tan@gmail.com virtual void takeOverFrom(BaseCPU *); 290180SN/A 291124SN/A /** 292124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 293124SN/A * This is a constant for the duration of the simulation. 294124SN/A */ 2956221Snate@binkert.org ThreadID numThreads; 2962SN/A 297124SN/A /** 298124SN/A * Vector of per-thread instruction-based event queues. Used for 299124SN/A * scheduling events based on number of instructions committed by 300124SN/A * a particular thread. 301124SN/A */ 302503SN/A EventQueue **comInstEventQueue; 3032SN/A 304124SN/A /** 305124SN/A * Vector of per-thread load-based event queues. Used for 306124SN/A * scheduling events based on number of loads committed by 307124SN/A *a particular thread. 308124SN/A */ 309124SN/A EventQueue **comLoadEventQueue; 310124SN/A 3112SN/A System *system; 312921SN/A 3133661Srdreslin@umich.edu Tick phase; 3143661Srdreslin@umich.edu 315921SN/A /** 316921SN/A * Serialize this object to the given output stream. 317921SN/A * @param os The stream to serialize to. 318921SN/A */ 319921SN/A virtual void serialize(std::ostream &os); 320921SN/A 321921SN/A /** 322921SN/A * Reconstruct the state of this object from a checkpoint. 323921SN/A * @param cp The checkpoint use. 324921SN/A * @param section The section name of this object 325921SN/A */ 326921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 327921SN/A 328124SN/A /** 329124SN/A * Return pointer to CPU's branch predictor (NULL if none). 330124SN/A * @return Branch predictor pointer. 331124SN/A */ 3322SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3332SN/A 3348834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 3358834Satgutier@umich.edu 3368834Satgutier@umich.edu virtual Counter totalOps() const = 0; 337707SN/A 3381191SN/A // Function tracing 3391191SN/A private: 3401191SN/A bool functionTracingEnabled; 3411191SN/A std::ostream *functionTraceStream; 3421191SN/A Addr currentFunctionStart; 3431191SN/A Addr currentFunctionEnd; 3441191SN/A Tick functionEntryTick; 3451191SN/A void enableFunctionTrace(); 3461191SN/A void traceFunctionsInternal(Addr pc); 3471191SN/A 3488662SAli.Saidi@ARM.com private: 3498662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3508662SAli.Saidi@ARM.com 3518662SAli.Saidi@ARM.com public: 3521191SN/A void traceFunctions(Addr pc) 3531191SN/A { 3541191SN/A if (functionTracingEnabled) 3551191SN/A traceFunctionsInternal(pc); 3561191SN/A } 3571191SN/A 3582SN/A static int numSimulatedCPUs() { return cpuList.size(); } 3598834Satgutier@umich.edu static Counter numSimulatedInsts() 360707SN/A { 361707SN/A Counter total = 0; 362707SN/A 363707SN/A int size = cpuList.size(); 364707SN/A for (int i = 0; i < size; ++i) 3658834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 3668834Satgutier@umich.edu 3678834Satgutier@umich.edu return total; 3688834Satgutier@umich.edu } 3698834Satgutier@umich.edu 3708834Satgutier@umich.edu static Counter numSimulatedOps() 3718834Satgutier@umich.edu { 3728834Satgutier@umich.edu Counter total = 0; 3738834Satgutier@umich.edu 3748834Satgutier@umich.edu int size = cpuList.size(); 3758834Satgutier@umich.edu for (int i = 0; i < size; ++i) 3768834Satgutier@umich.edu total += cpuList[i]->totalOps(); 377707SN/A 378707SN/A return total; 379707SN/A } 380707SN/A 381707SN/A public: 382707SN/A // Number of CPU cycles simulated 3835999Snate@binkert.org Stats::Scalar numCycles; 3847914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3857914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3862SN/A}; 3872SN/A 3881717SN/A#endif // __CPU_BASE_HH__ 389