base.hh revision 8786
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 317897Shestness@cs.utexas.edu * Rick Strong 322SN/A */ 332SN/A 341717SN/A#ifndef __CPU_BASE_HH__ 351717SN/A#define __CPU_BASE_HH__ 362SN/A 372SN/A#include <vector> 382SN/A 398745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 404182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 415664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 42707SN/A#include "base/statistics.hh" 431858SN/A#include "config/full_system.hh" 446658Snate@binkert.org#include "config/the_isa.hh" 458229Snate@binkert.org#include "mem/mem_object.hh" 4656SN/A#include "sim/eventq.hh" 478779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 484776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 492SN/A 505529Snate@binkert.orgclass BaseCPUParams; 512190SN/Aclass BranchPred; 522315SN/Aclass CheckerCPU; 532680Sktlim@umich.educlass ThreadContext; 542SN/Aclass System; 552856Srdreslin@umich.educlass Port; 562SN/A 574182Sgblack@eecs.umich.edunamespace TheISA 584182Sgblack@eecs.umich.edu{ 594182Sgblack@eecs.umich.edu class Predecoder; 604182Sgblack@eecs.umich.edu} 614182Sgblack@eecs.umich.edu 622356SN/Aclass CPUProgressEvent : public Event 632356SN/A{ 642356SN/A protected: 656144Sksewell@umich.edu Tick _interval; 662356SN/A Counter lastNumInst; 672356SN/A BaseCPU *cpu; 686144Sksewell@umich.edu bool _repeatEvent; 692356SN/A 702356SN/A public: 716144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 722356SN/A 732356SN/A void process(); 742356SN/A 756144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 766144Sksewell@umich.edu Tick interval() { return _interval; } 776144Sksewell@umich.edu 786144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 796144Sksewell@umich.edu 805336Shines@cs.fsu.edu virtual const char *description() const; 812356SN/A}; 822356SN/A 832856Srdreslin@umich.educlass BaseCPU : public MemObject 842SN/A{ 851634SN/A protected: 861634SN/A // CPU's clock period in terms of the number of ticks of curTime. 871695SN/A Tick clock; 883814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 893814Ssaidi@eecs.umich.edu Tick instCnt; 905712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 915712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 925715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 935712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 945712Shsul@eecs.umich.edu int _cpuId; 951634SN/A 961634SN/A public: 975712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 985712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 995712Shsul@eecs.umich.edu 1002359SN/A// Tick currentTick; 1017064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1025100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1037823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1045099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1057914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1067914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1073814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1083814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1091634SN/A 1103495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1113495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1127823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1133495Sktlim@umich.edu */ 1143495Sktlim@umich.edu Tick nextCycle(); 1153495Sktlim@umich.edu 1163495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1173495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1187823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1193495Sktlim@umich.edu * current cycle. 1203495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1213495Sktlim@umich.edu */ 1223495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1233495Sktlim@umich.edu 1245664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1255664Sgblack@eecs.umich.edu 1262SN/A protected: 1275704Snate@binkert.org TheISA::Interrupts *interrupts; 1282SN/A 1292SN/A public: 1305645Sgblack@eecs.umich.edu TheISA::Interrupts * 1315645Sgblack@eecs.umich.edu getInterruptController() 1325645Sgblack@eecs.umich.edu { 1335647Sgblack@eecs.umich.edu return interrupts; 1345645Sgblack@eecs.umich.edu } 1355645Sgblack@eecs.umich.edu 1365807Snate@binkert.org virtual void wakeup() = 0; 1375807Snate@binkert.org 1385807Snate@binkert.org void 1395807Snate@binkert.org postInterrupt(int int_num, int index) 1405807Snate@binkert.org { 1415807Snate@binkert.org interrupts->post(int_num, index); 1428779Sgblack@eecs.umich.edu if (FullSystem) 1438779Sgblack@eecs.umich.edu wakeup(); 1445807Snate@binkert.org } 1455807Snate@binkert.org 1465807Snate@binkert.org void 1475807Snate@binkert.org clearInterrupt(int int_num, int index) 1485807Snate@binkert.org { 1495807Snate@binkert.org interrupts->clear(int_num, index); 1505807Snate@binkert.org } 1515807Snate@binkert.org 1525807Snate@binkert.org void 1535807Snate@binkert.org clearInterrupts() 1545807Snate@binkert.org { 1555807Snate@binkert.org interrupts->clearAll(); 1565807Snate@binkert.org } 1572SN/A 1585704Snate@binkert.org bool 1595704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1605704Snate@binkert.org { 1615704Snate@binkert.org return interrupts->checkInterrupts(tc); 1625704Snate@binkert.org } 1631917SN/A 1641917SN/A class ProfileEvent : public Event 1651917SN/A { 1661917SN/A private: 1671917SN/A BaseCPU *cpu; 1685536Srstrong@hp.com Tick interval; 1691917SN/A 1701917SN/A public: 1715536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1721917SN/A void process(); 1731917SN/A }; 1741917SN/A ProfileEvent *profileEvent; 1752SN/A 1762SN/A protected: 1772680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1784182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1792SN/A 1804776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1814776Sgblack@eecs.umich.edu 1822SN/A public: 183393SN/A 1847764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1857764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1867764Sgblack@eecs.umich.edu 1874776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1884776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1894776Sgblack@eecs.umich.edu 190393SN/A /// Notify the CPU that the indicated context is now active. The 191393SN/A /// delay parameter indicates the number of ticks to wait before 192393SN/A /// executing (typically 0 or 1). 193393SN/A virtual void activateContext(int thread_num, int delay) {} 194393SN/A 195393SN/A /// Notify the CPU that the indicated context is now suspended. 196393SN/A virtual void suspendContext(int thread_num) {} 197393SN/A 198393SN/A /// Notify the CPU that the indicated context is now deallocated. 199393SN/A virtual void deallocateContext(int thread_num) {} 200393SN/A 201393SN/A /// Notify the CPU that the indicated context is now halted. 202393SN/A virtual void haltContext(int thread_num) {} 2032SN/A 2044000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2054000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2064000Ssaidi@eecs.umich.edu 2074000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2084000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2094000Ssaidi@eecs.umich.edu 2102SN/A public: 2115529Snate@binkert.org typedef BaseCPUParams Params; 2125529Snate@binkert.org const Params *params() const 2135529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2141400SN/A BaseCPU(Params *params); 2151191SN/A virtual ~BaseCPU(); 2162SN/A 2171129SN/A virtual void init(); 2181917SN/A virtual void startup(); 2192SN/A virtual void regStats(); 2202SN/A 2216221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2222103SN/A 2232680Sktlim@umich.edu void registerThreadContexts(); 224180SN/A 2251492SN/A /// Prepare for another CPU to take over execution. When it is 2261492SN/A /// is ready (drained pipe) it signals the sampler. 2272798Sktlim@umich.edu virtual void switchOut(); 228180SN/A 229180SN/A /// Take over execution from the given CPU. Used for warm-up and 230180SN/A /// sampling. 2314192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 232180SN/A 233124SN/A /** 234124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 235124SN/A * This is a constant for the duration of the simulation. 236124SN/A */ 2376221Snate@binkert.org ThreadID numThreads; 2382SN/A 239124SN/A /** 240124SN/A * Vector of per-thread instruction-based event queues. Used for 241124SN/A * scheduling events based on number of instructions committed by 242124SN/A * a particular thread. 243124SN/A */ 244503SN/A EventQueue **comInstEventQueue; 2452SN/A 246124SN/A /** 247124SN/A * Vector of per-thread load-based event queues. Used for 248124SN/A * scheduling events based on number of loads committed by 249124SN/A *a particular thread. 250124SN/A */ 251124SN/A EventQueue **comLoadEventQueue; 252124SN/A 2532SN/A System *system; 254921SN/A 2553661Srdreslin@umich.edu Tick phase; 2563661Srdreslin@umich.edu 257921SN/A /** 258921SN/A * Serialize this object to the given output stream. 259921SN/A * @param os The stream to serialize to. 260921SN/A */ 261921SN/A virtual void serialize(std::ostream &os); 262921SN/A 263921SN/A /** 264921SN/A * Reconstruct the state of this object from a checkpoint. 265921SN/A * @param cp The checkpoint use. 266921SN/A * @param section The section name of this object 267921SN/A */ 268921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 269921SN/A 270124SN/A /** 271124SN/A * Return pointer to CPU's branch predictor (NULL if none). 272124SN/A * @return Branch predictor pointer. 273124SN/A */ 2742SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2752SN/A 2766816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 277707SN/A 2781191SN/A // Function tracing 2791191SN/A private: 2801191SN/A bool functionTracingEnabled; 2811191SN/A std::ostream *functionTraceStream; 2821191SN/A Addr currentFunctionStart; 2831191SN/A Addr currentFunctionEnd; 2841191SN/A Tick functionEntryTick; 2851191SN/A void enableFunctionTrace(); 2861191SN/A void traceFunctionsInternal(Addr pc); 2871191SN/A 2881191SN/A protected: 2891191SN/A void traceFunctions(Addr pc) 2901191SN/A { 2911191SN/A if (functionTracingEnabled) 2921191SN/A traceFunctionsInternal(pc); 2931191SN/A } 2941191SN/A 2952SN/A private: 2962SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2972SN/A 2982SN/A public: 2992SN/A static int numSimulatedCPUs() { return cpuList.size(); } 300707SN/A static Counter numSimulatedInstructions() 301707SN/A { 302707SN/A Counter total = 0; 303707SN/A 304707SN/A int size = cpuList.size(); 305707SN/A for (int i = 0; i < size; ++i) 306707SN/A total += cpuList[i]->totalInstructions(); 307707SN/A 308707SN/A return total; 309707SN/A } 310707SN/A 311707SN/A public: 312707SN/A // Number of CPU cycles simulated 3135999Snate@binkert.org Stats::Scalar numCycles; 3147914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3157914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3162SN/A}; 3172SN/A 3181717SN/A#endif // __CPU_BASE_HH__ 319