base.hh revision 8745
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 317897Shestness@cs.utexas.edu * Rick Strong 322SN/A */ 332SN/A 341717SN/A#ifndef __CPU_BASE_HH__ 351717SN/A#define __CPU_BASE_HH__ 362SN/A 372SN/A#include <vector> 382SN/A 398745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 404182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 415664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 42707SN/A#include "base/statistics.hh" 431858SN/A#include "config/full_system.hh" 446658Snate@binkert.org#include "config/the_isa.hh" 458229Snate@binkert.org#include "mem/mem_object.hh" 4656SN/A#include "sim/eventq.hh" 474776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 482SN/A 495529Snate@binkert.orgclass BaseCPUParams; 502190SN/Aclass BranchPred; 512315SN/Aclass CheckerCPU; 522680Sktlim@umich.educlass ThreadContext; 532SN/Aclass System; 542856Srdreslin@umich.educlass Port; 552SN/A 564182Sgblack@eecs.umich.edunamespace TheISA 574182Sgblack@eecs.umich.edu{ 584182Sgblack@eecs.umich.edu class Predecoder; 594182Sgblack@eecs.umich.edu} 604182Sgblack@eecs.umich.edu 612356SN/Aclass CPUProgressEvent : public Event 622356SN/A{ 632356SN/A protected: 646144Sksewell@umich.edu Tick _interval; 652356SN/A Counter lastNumInst; 662356SN/A BaseCPU *cpu; 676144Sksewell@umich.edu bool _repeatEvent; 682356SN/A 692356SN/A public: 706144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 712356SN/A 722356SN/A void process(); 732356SN/A 746144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 756144Sksewell@umich.edu Tick interval() { return _interval; } 766144Sksewell@umich.edu 776144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 786144Sksewell@umich.edu 795336Shines@cs.fsu.edu virtual const char *description() const; 802356SN/A}; 812356SN/A 822856Srdreslin@umich.educlass BaseCPU : public MemObject 832SN/A{ 841634SN/A protected: 851634SN/A // CPU's clock period in terms of the number of ticks of curTime. 861695SN/A Tick clock; 873814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 883814Ssaidi@eecs.umich.edu Tick instCnt; 895712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 905712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 915715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 925712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 935712Shsul@eecs.umich.edu int _cpuId; 941634SN/A 951634SN/A public: 965712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 975712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 985712Shsul@eecs.umich.edu 992359SN/A// Tick currentTick; 1007064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1015100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1027823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1035099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1047914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1057914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1063814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1073814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1081634SN/A 1093495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1103495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1117823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1123495Sktlim@umich.edu */ 1133495Sktlim@umich.edu Tick nextCycle(); 1143495Sktlim@umich.edu 1153495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1163495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1177823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1183495Sktlim@umich.edu * current cycle. 1193495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1203495Sktlim@umich.edu */ 1213495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1223495Sktlim@umich.edu 1235664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1245664Sgblack@eecs.umich.edu 1252SN/A protected: 1265704Snate@binkert.org TheISA::Interrupts *interrupts; 1272SN/A 1282SN/A public: 1295645Sgblack@eecs.umich.edu TheISA::Interrupts * 1305645Sgblack@eecs.umich.edu getInterruptController() 1315645Sgblack@eecs.umich.edu { 1325647Sgblack@eecs.umich.edu return interrupts; 1335645Sgblack@eecs.umich.edu } 1345645Sgblack@eecs.umich.edu 1358745Sgblack@eecs.umich.edu#if FULL_SYSTEM 1365807Snate@binkert.org virtual void wakeup() = 0; 1378745Sgblack@eecs.umich.edu#endif 1385807Snate@binkert.org 1395807Snate@binkert.org void 1405807Snate@binkert.org postInterrupt(int int_num, int index) 1415807Snate@binkert.org { 1425807Snate@binkert.org interrupts->post(int_num, index); 1438745Sgblack@eecs.umich.edu#if FULL_SYSTEM 1445807Snate@binkert.org wakeup(); 1458745Sgblack@eecs.umich.edu#endif 1465807Snate@binkert.org } 1475807Snate@binkert.org 1485807Snate@binkert.org void 1495807Snate@binkert.org clearInterrupt(int int_num, int index) 1505807Snate@binkert.org { 1515807Snate@binkert.org interrupts->clear(int_num, index); 1525807Snate@binkert.org } 1535807Snate@binkert.org 1545807Snate@binkert.org void 1555807Snate@binkert.org clearInterrupts() 1565807Snate@binkert.org { 1575807Snate@binkert.org interrupts->clearAll(); 1585807Snate@binkert.org } 1592SN/A 1605704Snate@binkert.org bool 1615704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1625704Snate@binkert.org { 1635704Snate@binkert.org return interrupts->checkInterrupts(tc); 1645704Snate@binkert.org } 1651917SN/A 1661917SN/A class ProfileEvent : public Event 1671917SN/A { 1681917SN/A private: 1691917SN/A BaseCPU *cpu; 1705536Srstrong@hp.com Tick interval; 1711917SN/A 1721917SN/A public: 1735536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1741917SN/A void process(); 1751917SN/A }; 1761917SN/A ProfileEvent *profileEvent; 1772SN/A 1782SN/A protected: 1792680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1804182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1812SN/A 1824776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1834776Sgblack@eecs.umich.edu 1842SN/A public: 185393SN/A 1867764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1877764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1887764Sgblack@eecs.umich.edu 1894776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1904776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1914776Sgblack@eecs.umich.edu 192393SN/A /// Notify the CPU that the indicated context is now active. The 193393SN/A /// delay parameter indicates the number of ticks to wait before 194393SN/A /// executing (typically 0 or 1). 195393SN/A virtual void activateContext(int thread_num, int delay) {} 196393SN/A 197393SN/A /// Notify the CPU that the indicated context is now suspended. 198393SN/A virtual void suspendContext(int thread_num) {} 199393SN/A 200393SN/A /// Notify the CPU that the indicated context is now deallocated. 201393SN/A virtual void deallocateContext(int thread_num) {} 202393SN/A 203393SN/A /// Notify the CPU that the indicated context is now halted. 204393SN/A virtual void haltContext(int thread_num) {} 2052SN/A 2064000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2074000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2084000Ssaidi@eecs.umich.edu 2094000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2104000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2114000Ssaidi@eecs.umich.edu 2122SN/A public: 2135529Snate@binkert.org typedef BaseCPUParams Params; 2145529Snate@binkert.org const Params *params() const 2155529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2161400SN/A BaseCPU(Params *params); 2171191SN/A virtual ~BaseCPU(); 2182SN/A 2191129SN/A virtual void init(); 2201917SN/A virtual void startup(); 2212SN/A virtual void regStats(); 2222SN/A 2236221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2242103SN/A 2252680Sktlim@umich.edu void registerThreadContexts(); 226180SN/A 2271492SN/A /// Prepare for another CPU to take over execution. When it is 2281492SN/A /// is ready (drained pipe) it signals the sampler. 2292798Sktlim@umich.edu virtual void switchOut(); 230180SN/A 231180SN/A /// Take over execution from the given CPU. Used for warm-up and 232180SN/A /// sampling. 2334192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 234180SN/A 235124SN/A /** 236124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 237124SN/A * This is a constant for the duration of the simulation. 238124SN/A */ 2396221Snate@binkert.org ThreadID numThreads; 2402SN/A 241124SN/A /** 242124SN/A * Vector of per-thread instruction-based event queues. Used for 243124SN/A * scheduling events based on number of instructions committed by 244124SN/A * a particular thread. 245124SN/A */ 246503SN/A EventQueue **comInstEventQueue; 2472SN/A 248124SN/A /** 249124SN/A * Vector of per-thread load-based event queues. Used for 250124SN/A * scheduling events based on number of loads committed by 251124SN/A *a particular thread. 252124SN/A */ 253124SN/A EventQueue **comLoadEventQueue; 254124SN/A 2552SN/A System *system; 256921SN/A 2573661Srdreslin@umich.edu Tick phase; 2583661Srdreslin@umich.edu 259921SN/A /** 260921SN/A * Serialize this object to the given output stream. 261921SN/A * @param os The stream to serialize to. 262921SN/A */ 263921SN/A virtual void serialize(std::ostream &os); 264921SN/A 265921SN/A /** 266921SN/A * Reconstruct the state of this object from a checkpoint. 267921SN/A * @param cp The checkpoint use. 268921SN/A * @param section The section name of this object 269921SN/A */ 270921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 271921SN/A 272124SN/A /** 273124SN/A * Return pointer to CPU's branch predictor (NULL if none). 274124SN/A * @return Branch predictor pointer. 275124SN/A */ 2762SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2772SN/A 2786816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 279707SN/A 2801191SN/A // Function tracing 2811191SN/A private: 2821191SN/A bool functionTracingEnabled; 2831191SN/A std::ostream *functionTraceStream; 2841191SN/A Addr currentFunctionStart; 2851191SN/A Addr currentFunctionEnd; 2861191SN/A Tick functionEntryTick; 2871191SN/A void enableFunctionTrace(); 2881191SN/A void traceFunctionsInternal(Addr pc); 2891191SN/A 2901191SN/A protected: 2911191SN/A void traceFunctions(Addr pc) 2921191SN/A { 2931191SN/A if (functionTracingEnabled) 2941191SN/A traceFunctionsInternal(pc); 2951191SN/A } 2961191SN/A 2972SN/A private: 2982SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2992SN/A 3002SN/A public: 3012SN/A static int numSimulatedCPUs() { return cpuList.size(); } 302707SN/A static Counter numSimulatedInstructions() 303707SN/A { 304707SN/A Counter total = 0; 305707SN/A 306707SN/A int size = cpuList.size(); 307707SN/A for (int i = 0; i < size; ++i) 308707SN/A total += cpuList[i]->totalInstructions(); 309707SN/A 310707SN/A return total; 311707SN/A } 312707SN/A 313707SN/A public: 314707SN/A // Number of CPU cycles simulated 3155999Snate@binkert.org Stats::Scalar numCycles; 3167914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3177914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3182SN/A}; 3192SN/A 3201717SN/A#endif // __CPU_BASE_HH__ 321