base.hh revision 8711
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 514182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 525664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 53707SN/A#include "base/statistics.hh" 541858SN/A#include "config/full_system.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 584776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 592SN/A 603520Sgblack@eecs.umich.edu#if FULL_SYSTEM 613520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 623520Sgblack@eecs.umich.edu#endif 633520Sgblack@eecs.umich.edu 645529Snate@binkert.orgclass BaseCPUParams; 652190SN/Aclass BranchPred; 662315SN/Aclass CheckerCPU; 672680Sktlim@umich.educlass ThreadContext; 682SN/Aclass System; 692856Srdreslin@umich.educlass Port; 702SN/A 714182Sgblack@eecs.umich.edunamespace TheISA 724182Sgblack@eecs.umich.edu{ 734182Sgblack@eecs.umich.edu class Predecoder; 744182Sgblack@eecs.umich.edu} 754182Sgblack@eecs.umich.edu 762356SN/Aclass CPUProgressEvent : public Event 772356SN/A{ 782356SN/A protected: 796144Sksewell@umich.edu Tick _interval; 802356SN/A Counter lastNumInst; 812356SN/A BaseCPU *cpu; 826144Sksewell@umich.edu bool _repeatEvent; 832356SN/A 842356SN/A public: 856144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 862356SN/A 872356SN/A void process(); 882356SN/A 896144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 906144Sksewell@umich.edu Tick interval() { return _interval; } 916144Sksewell@umich.edu 926144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 936144Sksewell@umich.edu 945336Shines@cs.fsu.edu virtual const char *description() const; 952356SN/A}; 962356SN/A 972856Srdreslin@umich.educlass BaseCPU : public MemObject 982SN/A{ 991634SN/A protected: 1001634SN/A // CPU's clock period in terms of the number of ticks of curTime. 1011695SN/A Tick clock; 1023814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1033814Ssaidi@eecs.umich.edu Tick instCnt; 1045712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1055712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1065715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1075712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1085712Shsul@eecs.umich.edu int _cpuId; 1091634SN/A 1108707Sandreas.hansson@arm.com /** 1118707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1128707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1138707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1148707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1158707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1168707Sandreas.hansson@arm.com * subclasses have to override these methods. 1178707Sandreas.hansson@arm.com */ 1188707Sandreas.hansson@arm.com class CpuPort : public Port 1198707Sandreas.hansson@arm.com { 1208707Sandreas.hansson@arm.com public: 1218707Sandreas.hansson@arm.com 1228707Sandreas.hansson@arm.com /** 1238707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1248707Sandreas.hansson@arm.com * 1258707Sandreas.hansson@arm.com * @param _name port name including the owner 1268707Sandreas.hansson@arm.com * @param _name structural owner of this port 1278707Sandreas.hansson@arm.com */ 1288707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1298711Sandreas.hansson@arm.com Port(_name, _owner) 1308707Sandreas.hansson@arm.com { } 1318707Sandreas.hansson@arm.com 1328707Sandreas.hansson@arm.com protected: 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1358707Sandreas.hansson@arm.com 1368707Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 1378707Sandreas.hansson@arm.com 1388707Sandreas.hansson@arm.com virtual void recvRetry(); 1398707Sandreas.hansson@arm.com 1408707Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 1418707Sandreas.hansson@arm.com 1428711Sandreas.hansson@arm.com void recvRangeChange(); 1438707Sandreas.hansson@arm.com 1448707Sandreas.hansson@arm.com }; 1458707Sandreas.hansson@arm.com 1461634SN/A public: 1475712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1485712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1495712Shsul@eecs.umich.edu 1502359SN/A// Tick currentTick; 1517064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1525100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1537823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1545099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1557914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1567914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1573814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1583814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1591634SN/A 1603495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1613495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1627823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1633495Sktlim@umich.edu */ 1643495Sktlim@umich.edu Tick nextCycle(); 1653495Sktlim@umich.edu 1663495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1673495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1687823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1693495Sktlim@umich.edu * current cycle. 1703495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1713495Sktlim@umich.edu */ 1723495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1733495Sktlim@umich.edu 1745664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1755664Sgblack@eecs.umich.edu 1761858SN/A#if FULL_SYSTEM 1772SN/A protected: 1785704Snate@binkert.org TheISA::Interrupts *interrupts; 1792SN/A 1802SN/A public: 1815645Sgblack@eecs.umich.edu TheISA::Interrupts * 1825645Sgblack@eecs.umich.edu getInterruptController() 1835645Sgblack@eecs.umich.edu { 1845647Sgblack@eecs.umich.edu return interrupts; 1855645Sgblack@eecs.umich.edu } 1865645Sgblack@eecs.umich.edu 1875807Snate@binkert.org virtual void wakeup() = 0; 1885807Snate@binkert.org 1895807Snate@binkert.org void 1905807Snate@binkert.org postInterrupt(int int_num, int index) 1915807Snate@binkert.org { 1925807Snate@binkert.org interrupts->post(int_num, index); 1935807Snate@binkert.org wakeup(); 1945807Snate@binkert.org } 1955807Snate@binkert.org 1965807Snate@binkert.org void 1975807Snate@binkert.org clearInterrupt(int int_num, int index) 1985807Snate@binkert.org { 1995807Snate@binkert.org interrupts->clear(int_num, index); 2005807Snate@binkert.org } 2015807Snate@binkert.org 2025807Snate@binkert.org void 2035807Snate@binkert.org clearInterrupts() 2045807Snate@binkert.org { 2055807Snate@binkert.org interrupts->clearAll(); 2065807Snate@binkert.org } 2072SN/A 2085704Snate@binkert.org bool 2095704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2105704Snate@binkert.org { 2115704Snate@binkert.org return interrupts->checkInterrupts(tc); 2125704Snate@binkert.org } 2131917SN/A 2141917SN/A class ProfileEvent : public Event 2151917SN/A { 2161917SN/A private: 2171917SN/A BaseCPU *cpu; 2185536Srstrong@hp.com Tick interval; 2191917SN/A 2201917SN/A public: 2215536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2221917SN/A void process(); 2231917SN/A }; 2241917SN/A ProfileEvent *profileEvent; 2252SN/A#endif 2262SN/A 2272SN/A protected: 2282680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2294182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 2302SN/A 2314776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2324776Sgblack@eecs.umich.edu 2332SN/A public: 234393SN/A 2357764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2367764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2377764Sgblack@eecs.umich.edu 2384776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2394776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2404776Sgblack@eecs.umich.edu 241393SN/A /// Notify the CPU that the indicated context is now active. The 242393SN/A /// delay parameter indicates the number of ticks to wait before 243393SN/A /// executing (typically 0 or 1). 244393SN/A virtual void activateContext(int thread_num, int delay) {} 245393SN/A 246393SN/A /// Notify the CPU that the indicated context is now suspended. 247393SN/A virtual void suspendContext(int thread_num) {} 248393SN/A 249393SN/A /// Notify the CPU that the indicated context is now deallocated. 250393SN/A virtual void deallocateContext(int thread_num) {} 251393SN/A 252393SN/A /// Notify the CPU that the indicated context is now halted. 253393SN/A virtual void haltContext(int thread_num) {} 2542SN/A 2554000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2564000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2574000Ssaidi@eecs.umich.edu 2584000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2594000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2604000Ssaidi@eecs.umich.edu 2612SN/A public: 2625529Snate@binkert.org typedef BaseCPUParams Params; 2635529Snate@binkert.org const Params *params() const 2645529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2651400SN/A BaseCPU(Params *params); 2661191SN/A virtual ~BaseCPU(); 2672SN/A 2681129SN/A virtual void init(); 2691917SN/A virtual void startup(); 2702SN/A virtual void regStats(); 2712SN/A 2726221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2732103SN/A 2742680Sktlim@umich.edu void registerThreadContexts(); 275180SN/A 2761492SN/A /// Prepare for another CPU to take over execution. When it is 2771492SN/A /// is ready (drained pipe) it signals the sampler. 2782798Sktlim@umich.edu virtual void switchOut(); 279180SN/A 280180SN/A /// Take over execution from the given CPU. Used for warm-up and 281180SN/A /// sampling. 2824192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 283180SN/A 284124SN/A /** 285124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 286124SN/A * This is a constant for the duration of the simulation. 287124SN/A */ 2886221Snate@binkert.org ThreadID numThreads; 2892SN/A 290124SN/A /** 291124SN/A * Vector of per-thread instruction-based event queues. Used for 292124SN/A * scheduling events based on number of instructions committed by 293124SN/A * a particular thread. 294124SN/A */ 295503SN/A EventQueue **comInstEventQueue; 2962SN/A 297124SN/A /** 298124SN/A * Vector of per-thread load-based event queues. Used for 299124SN/A * scheduling events based on number of loads committed by 300124SN/A *a particular thread. 301124SN/A */ 302124SN/A EventQueue **comLoadEventQueue; 303124SN/A 3042SN/A System *system; 305921SN/A 3063661Srdreslin@umich.edu Tick phase; 3073661Srdreslin@umich.edu 3082378SN/A#if FULL_SYSTEM 309921SN/A /** 310921SN/A * Serialize this object to the given output stream. 311921SN/A * @param os The stream to serialize to. 312921SN/A */ 313921SN/A virtual void serialize(std::ostream &os); 314921SN/A 315921SN/A /** 316921SN/A * Reconstruct the state of this object from a checkpoint. 317921SN/A * @param cp The checkpoint use. 318921SN/A * @param section The section name of this object 319921SN/A */ 320921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 321921SN/A 3222SN/A#endif 3232SN/A 324124SN/A /** 325124SN/A * Return pointer to CPU's branch predictor (NULL if none). 326124SN/A * @return Branch predictor pointer. 327124SN/A */ 3282SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3292SN/A 3306816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 331707SN/A 3321191SN/A // Function tracing 3331191SN/A private: 3341191SN/A bool functionTracingEnabled; 3351191SN/A std::ostream *functionTraceStream; 3361191SN/A Addr currentFunctionStart; 3371191SN/A Addr currentFunctionEnd; 3381191SN/A Tick functionEntryTick; 3391191SN/A void enableFunctionTrace(); 3401191SN/A void traceFunctionsInternal(Addr pc); 3411191SN/A 3428662SAli.Saidi@ARM.com private: 3438662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3448662SAli.Saidi@ARM.com 3458662SAli.Saidi@ARM.com public: 3461191SN/A void traceFunctions(Addr pc) 3471191SN/A { 3481191SN/A if (functionTracingEnabled) 3491191SN/A traceFunctionsInternal(pc); 3501191SN/A } 3511191SN/A 3522SN/A static int numSimulatedCPUs() { return cpuList.size(); } 353707SN/A static Counter numSimulatedInstructions() 354707SN/A { 355707SN/A Counter total = 0; 356707SN/A 357707SN/A int size = cpuList.size(); 358707SN/A for (int i = 0; i < size; ++i) 359707SN/A total += cpuList[i]->totalInstructions(); 360707SN/A 361707SN/A return total; 362707SN/A } 363707SN/A 364707SN/A public: 365707SN/A // Number of CPU cycles simulated 3665999Snate@binkert.org Stats::Scalar numCycles; 3677914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3687914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3692SN/A}; 3702SN/A 3711717SN/A#endif // __CPU_BASE_HH__ 372