base.hh revision 8707
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 514182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 525664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 53707SN/A#include "base/statistics.hh" 541858SN/A#include "config/full_system.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "mem/mem_object.hh" 5756SN/A#include "sim/eventq.hh" 584776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 592SN/A 603520Sgblack@eecs.umich.edu#if FULL_SYSTEM 613520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 623520Sgblack@eecs.umich.edu#endif 633520Sgblack@eecs.umich.edu 645529Snate@binkert.orgclass BaseCPUParams; 652190SN/Aclass BranchPred; 662315SN/Aclass CheckerCPU; 672680Sktlim@umich.educlass ThreadContext; 682SN/Aclass System; 692856Srdreslin@umich.educlass Port; 702SN/A 714182Sgblack@eecs.umich.edunamespace TheISA 724182Sgblack@eecs.umich.edu{ 734182Sgblack@eecs.umich.edu class Predecoder; 744182Sgblack@eecs.umich.edu} 754182Sgblack@eecs.umich.edu 762356SN/Aclass CPUProgressEvent : public Event 772356SN/A{ 782356SN/A protected: 796144Sksewell@umich.edu Tick _interval; 802356SN/A Counter lastNumInst; 812356SN/A BaseCPU *cpu; 826144Sksewell@umich.edu bool _repeatEvent; 832356SN/A 842356SN/A public: 856144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 862356SN/A 872356SN/A void process(); 882356SN/A 896144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 906144Sksewell@umich.edu Tick interval() { return _interval; } 916144Sksewell@umich.edu 926144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 936144Sksewell@umich.edu 945336Shines@cs.fsu.edu virtual const char *description() const; 952356SN/A}; 962356SN/A 972856Srdreslin@umich.educlass BaseCPU : public MemObject 982SN/A{ 991634SN/A protected: 1001634SN/A // CPU's clock period in terms of the number of ticks of curTime. 1011695SN/A Tick clock; 1023814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1033814Ssaidi@eecs.umich.edu Tick instCnt; 1045712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1055712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1065715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1075712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1085712Shsul@eecs.umich.edu int _cpuId; 1091634SN/A 1108707Sandreas.hansson@arm.com /** 1118707Sandreas.hansson@arm.com * Define a base class for the CPU ports (instruction and data) 1128707Sandreas.hansson@arm.com * that is refined in the subclasses. This class handles the 1138707Sandreas.hansson@arm.com * common cases, i.e. the functional accesses and the status 1148707Sandreas.hansson@arm.com * changes and address range queries. The default behaviour for 1158707Sandreas.hansson@arm.com * both atomic and timing access is to panic and the corresponding 1168707Sandreas.hansson@arm.com * subclasses have to override these methods. 1178707Sandreas.hansson@arm.com */ 1188707Sandreas.hansson@arm.com class CpuPort : public Port 1198707Sandreas.hansson@arm.com { 1208707Sandreas.hansson@arm.com public: 1218707Sandreas.hansson@arm.com 1228707Sandreas.hansson@arm.com /** 1238707Sandreas.hansson@arm.com * Create a CPU port with a name and a structural owner. 1248707Sandreas.hansson@arm.com * 1258707Sandreas.hansson@arm.com * @param _name port name including the owner 1268707Sandreas.hansson@arm.com * @param _name structural owner of this port 1278707Sandreas.hansson@arm.com */ 1288707Sandreas.hansson@arm.com CpuPort(const std::string& _name, MemObject* _owner) : 1298707Sandreas.hansson@arm.com Port(_name, _owner), snoopRangeSent(false) 1308707Sandreas.hansson@arm.com { } 1318707Sandreas.hansson@arm.com 1328707Sandreas.hansson@arm.com protected: 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com virtual bool recvTiming(PacketPtr pkt); 1358707Sandreas.hansson@arm.com 1368707Sandreas.hansson@arm.com virtual Tick recvAtomic(PacketPtr pkt); 1378707Sandreas.hansson@arm.com 1388707Sandreas.hansson@arm.com virtual void recvRetry(); 1398707Sandreas.hansson@arm.com 1408707Sandreas.hansson@arm.com void recvFunctional(PacketPtr pkt); 1418707Sandreas.hansson@arm.com 1428707Sandreas.hansson@arm.com void recvStatusChange(Status status); 1438707Sandreas.hansson@arm.com 1448707Sandreas.hansson@arm.com /** 1458707Sandreas.hansson@arm.com * Add CPU ports are master ports and do not respond to any 1468707Sandreas.hansson@arm.com * address ranges. Note that the LSQ snoops for specific ISAs 1478707Sandreas.hansson@arm.com * and thus has to override this method. 1488707Sandreas.hansson@arm.com * 1498707Sandreas.hansson@arm.com * @param resp list of ranges this port responds to 1508707Sandreas.hansson@arm.com * @param snoop indicating if the port snoops or not 1518707Sandreas.hansson@arm.com */ 1528707Sandreas.hansson@arm.com virtual void getDeviceAddressRanges(AddrRangeList& resp, 1538707Sandreas.hansson@arm.com bool& snoop); 1548707Sandreas.hansson@arm.com 1558707Sandreas.hansson@arm.com private: 1568707Sandreas.hansson@arm.com 1578707Sandreas.hansson@arm.com bool snoopRangeSent; 1588707Sandreas.hansson@arm.com 1598707Sandreas.hansson@arm.com }; 1608707Sandreas.hansson@arm.com 1611634SN/A public: 1625712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1635712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1645712Shsul@eecs.umich.edu 1652359SN/A// Tick currentTick; 1667064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1675100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1687823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1695099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1707914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1717914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1723814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1733814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1741634SN/A 1753495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1763495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1777823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1783495Sktlim@umich.edu */ 1793495Sktlim@umich.edu Tick nextCycle(); 1803495Sktlim@umich.edu 1813495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1823495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1837823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1843495Sktlim@umich.edu * current cycle. 1853495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1863495Sktlim@umich.edu */ 1873495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1883495Sktlim@umich.edu 1895664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1905664Sgblack@eecs.umich.edu 1911858SN/A#if FULL_SYSTEM 1922SN/A protected: 1935704Snate@binkert.org TheISA::Interrupts *interrupts; 1942SN/A 1952SN/A public: 1965645Sgblack@eecs.umich.edu TheISA::Interrupts * 1975645Sgblack@eecs.umich.edu getInterruptController() 1985645Sgblack@eecs.umich.edu { 1995647Sgblack@eecs.umich.edu return interrupts; 2005645Sgblack@eecs.umich.edu } 2015645Sgblack@eecs.umich.edu 2025807Snate@binkert.org virtual void wakeup() = 0; 2035807Snate@binkert.org 2045807Snate@binkert.org void 2055807Snate@binkert.org postInterrupt(int int_num, int index) 2065807Snate@binkert.org { 2075807Snate@binkert.org interrupts->post(int_num, index); 2085807Snate@binkert.org wakeup(); 2095807Snate@binkert.org } 2105807Snate@binkert.org 2115807Snate@binkert.org void 2125807Snate@binkert.org clearInterrupt(int int_num, int index) 2135807Snate@binkert.org { 2145807Snate@binkert.org interrupts->clear(int_num, index); 2155807Snate@binkert.org } 2165807Snate@binkert.org 2175807Snate@binkert.org void 2185807Snate@binkert.org clearInterrupts() 2195807Snate@binkert.org { 2205807Snate@binkert.org interrupts->clearAll(); 2215807Snate@binkert.org } 2222SN/A 2235704Snate@binkert.org bool 2245704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2255704Snate@binkert.org { 2265704Snate@binkert.org return interrupts->checkInterrupts(tc); 2275704Snate@binkert.org } 2281917SN/A 2291917SN/A class ProfileEvent : public Event 2301917SN/A { 2311917SN/A private: 2321917SN/A BaseCPU *cpu; 2335536Srstrong@hp.com Tick interval; 2341917SN/A 2351917SN/A public: 2365536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2371917SN/A void process(); 2381917SN/A }; 2391917SN/A ProfileEvent *profileEvent; 2402SN/A#endif 2412SN/A 2422SN/A protected: 2432680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2444182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 2452SN/A 2464776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2474776Sgblack@eecs.umich.edu 2482SN/A public: 249393SN/A 2507764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2517764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2527764Sgblack@eecs.umich.edu 2534776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2544776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2554776Sgblack@eecs.umich.edu 256393SN/A /// Notify the CPU that the indicated context is now active. The 257393SN/A /// delay parameter indicates the number of ticks to wait before 258393SN/A /// executing (typically 0 or 1). 259393SN/A virtual void activateContext(int thread_num, int delay) {} 260393SN/A 261393SN/A /// Notify the CPU that the indicated context is now suspended. 262393SN/A virtual void suspendContext(int thread_num) {} 263393SN/A 264393SN/A /// Notify the CPU that the indicated context is now deallocated. 265393SN/A virtual void deallocateContext(int thread_num) {} 266393SN/A 267393SN/A /// Notify the CPU that the indicated context is now halted. 268393SN/A virtual void haltContext(int thread_num) {} 2692SN/A 2704000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2714000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2724000Ssaidi@eecs.umich.edu 2734000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2744000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2754000Ssaidi@eecs.umich.edu 2762SN/A public: 2775529Snate@binkert.org typedef BaseCPUParams Params; 2785529Snate@binkert.org const Params *params() const 2795529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2801400SN/A BaseCPU(Params *params); 2811191SN/A virtual ~BaseCPU(); 2822SN/A 2831129SN/A virtual void init(); 2841917SN/A virtual void startup(); 2852SN/A virtual void regStats(); 2862SN/A 2876221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2882103SN/A 2892680Sktlim@umich.edu void registerThreadContexts(); 290180SN/A 2911492SN/A /// Prepare for another CPU to take over execution. When it is 2921492SN/A /// is ready (drained pipe) it signals the sampler. 2932798Sktlim@umich.edu virtual void switchOut(); 294180SN/A 295180SN/A /// Take over execution from the given CPU. Used for warm-up and 296180SN/A /// sampling. 2974192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 298180SN/A 299124SN/A /** 300124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 301124SN/A * This is a constant for the duration of the simulation. 302124SN/A */ 3036221Snate@binkert.org ThreadID numThreads; 3042SN/A 305124SN/A /** 306124SN/A * Vector of per-thread instruction-based event queues. Used for 307124SN/A * scheduling events based on number of instructions committed by 308124SN/A * a particular thread. 309124SN/A */ 310503SN/A EventQueue **comInstEventQueue; 3112SN/A 312124SN/A /** 313124SN/A * Vector of per-thread load-based event queues. Used for 314124SN/A * scheduling events based on number of loads committed by 315124SN/A *a particular thread. 316124SN/A */ 317124SN/A EventQueue **comLoadEventQueue; 318124SN/A 3192SN/A System *system; 320921SN/A 3213661Srdreslin@umich.edu Tick phase; 3223661Srdreslin@umich.edu 3232378SN/A#if FULL_SYSTEM 324921SN/A /** 325921SN/A * Serialize this object to the given output stream. 326921SN/A * @param os The stream to serialize to. 327921SN/A */ 328921SN/A virtual void serialize(std::ostream &os); 329921SN/A 330921SN/A /** 331921SN/A * Reconstruct the state of this object from a checkpoint. 332921SN/A * @param cp The checkpoint use. 333921SN/A * @param section The section name of this object 334921SN/A */ 335921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 336921SN/A 3372SN/A#endif 3382SN/A 339124SN/A /** 340124SN/A * Return pointer to CPU's branch predictor (NULL if none). 341124SN/A * @return Branch predictor pointer. 342124SN/A */ 3432SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3442SN/A 3456816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 346707SN/A 3471191SN/A // Function tracing 3481191SN/A private: 3491191SN/A bool functionTracingEnabled; 3501191SN/A std::ostream *functionTraceStream; 3511191SN/A Addr currentFunctionStart; 3521191SN/A Addr currentFunctionEnd; 3531191SN/A Tick functionEntryTick; 3541191SN/A void enableFunctionTrace(); 3551191SN/A void traceFunctionsInternal(Addr pc); 3561191SN/A 3578662SAli.Saidi@ARM.com private: 3588662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3598662SAli.Saidi@ARM.com 3608662SAli.Saidi@ARM.com public: 3611191SN/A void traceFunctions(Addr pc) 3621191SN/A { 3631191SN/A if (functionTracingEnabled) 3641191SN/A traceFunctionsInternal(pc); 3651191SN/A } 3661191SN/A 3672SN/A static int numSimulatedCPUs() { return cpuList.size(); } 368707SN/A static Counter numSimulatedInstructions() 369707SN/A { 370707SN/A Counter total = 0; 371707SN/A 372707SN/A int size = cpuList.size(); 373707SN/A for (int i = 0; i < size; ++i) 374707SN/A total += cpuList[i]->totalInstructions(); 375707SN/A 376707SN/A return total; 377707SN/A } 378707SN/A 379707SN/A public: 380707SN/A // Number of CPU cycles simulated 3815999Snate@binkert.org Stats::Scalar numCycles; 3827914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3837914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3842SN/A}; 3852SN/A 3861717SN/A#endif // __CPU_BASE_HH__ 387