base.hh revision 8229
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 317897Shestness@cs.utexas.edu * Rick Strong 322SN/A */ 332SN/A 341717SN/A#ifndef __CPU_BASE_HH__ 351717SN/A#define __CPU_BASE_HH__ 362SN/A 372SN/A#include <vector> 382SN/A 394182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 405664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 41707SN/A#include "base/statistics.hh" 421858SN/A#include "config/full_system.hh" 436658Snate@binkert.org#include "config/the_isa.hh" 448229Snate@binkert.org#include "mem/mem_object.hh" 4556SN/A#include "sim/eventq.hh" 464776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 472SN/A 483520Sgblack@eecs.umich.edu#if FULL_SYSTEM 493520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 503520Sgblack@eecs.umich.edu#endif 513520Sgblack@eecs.umich.edu 525529Snate@binkert.orgclass BaseCPUParams; 532190SN/Aclass BranchPred; 542315SN/Aclass CheckerCPU; 552680Sktlim@umich.educlass ThreadContext; 562SN/Aclass System; 572856Srdreslin@umich.educlass Port; 582SN/A 594182Sgblack@eecs.umich.edunamespace TheISA 604182Sgblack@eecs.umich.edu{ 614182Sgblack@eecs.umich.edu class Predecoder; 624182Sgblack@eecs.umich.edu} 634182Sgblack@eecs.umich.edu 642356SN/Aclass CPUProgressEvent : public Event 652356SN/A{ 662356SN/A protected: 676144Sksewell@umich.edu Tick _interval; 682356SN/A Counter lastNumInst; 692356SN/A BaseCPU *cpu; 706144Sksewell@umich.edu bool _repeatEvent; 712356SN/A 722356SN/A public: 736144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 742356SN/A 752356SN/A void process(); 762356SN/A 776144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 786144Sksewell@umich.edu Tick interval() { return _interval; } 796144Sksewell@umich.edu 806144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 816144Sksewell@umich.edu 825336Shines@cs.fsu.edu virtual const char *description() const; 832356SN/A}; 842356SN/A 852856Srdreslin@umich.educlass BaseCPU : public MemObject 862SN/A{ 871634SN/A protected: 881634SN/A // CPU's clock period in terms of the number of ticks of curTime. 891695SN/A Tick clock; 903814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 913814Ssaidi@eecs.umich.edu Tick instCnt; 925712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 935712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 945715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 955712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 965712Shsul@eecs.umich.edu int _cpuId; 971634SN/A 981634SN/A public: 995712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 1005712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 1015712Shsul@eecs.umich.edu 1022359SN/A// Tick currentTick; 1037064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1045100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1057823Ssteve.reinhardt@amd.com inline Tick curCycle() const { return curTick() / clock; } 1065099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1077914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1087914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1093814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1103814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1111634SN/A 1123495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1133495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1147823Ssteve.reinhardt@amd.com * may return curTick() if the CPU should run on the current cycle. 1153495Sktlim@umich.edu */ 1163495Sktlim@umich.edu Tick nextCycle(); 1173495Sktlim@umich.edu 1183495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1193495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1207823Ssteve.reinhardt@amd.com * function may return curTick() if the CPU should run on the 1213495Sktlim@umich.edu * current cycle. 1223495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1233495Sktlim@umich.edu */ 1243495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1253495Sktlim@umich.edu 1265664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1275664Sgblack@eecs.umich.edu 1281858SN/A#if FULL_SYSTEM 1292SN/A protected: 1305704Snate@binkert.org TheISA::Interrupts *interrupts; 1312SN/A 1322SN/A public: 1335645Sgblack@eecs.umich.edu TheISA::Interrupts * 1345645Sgblack@eecs.umich.edu getInterruptController() 1355645Sgblack@eecs.umich.edu { 1365647Sgblack@eecs.umich.edu return interrupts; 1375645Sgblack@eecs.umich.edu } 1385645Sgblack@eecs.umich.edu 1395807Snate@binkert.org virtual void wakeup() = 0; 1405807Snate@binkert.org 1415807Snate@binkert.org void 1425807Snate@binkert.org postInterrupt(int int_num, int index) 1435807Snate@binkert.org { 1445807Snate@binkert.org interrupts->post(int_num, index); 1455807Snate@binkert.org wakeup(); 1465807Snate@binkert.org } 1475807Snate@binkert.org 1485807Snate@binkert.org void 1495807Snate@binkert.org clearInterrupt(int int_num, int index) 1505807Snate@binkert.org { 1515807Snate@binkert.org interrupts->clear(int_num, index); 1525807Snate@binkert.org } 1535807Snate@binkert.org 1545807Snate@binkert.org void 1555807Snate@binkert.org clearInterrupts() 1565807Snate@binkert.org { 1575807Snate@binkert.org interrupts->clearAll(); 1585807Snate@binkert.org } 1592SN/A 1605704Snate@binkert.org bool 1615704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1625704Snate@binkert.org { 1635704Snate@binkert.org return interrupts->checkInterrupts(tc); 1645704Snate@binkert.org } 1651917SN/A 1661917SN/A class ProfileEvent : public Event 1671917SN/A { 1681917SN/A private: 1691917SN/A BaseCPU *cpu; 1705536Srstrong@hp.com Tick interval; 1711917SN/A 1721917SN/A public: 1735536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1741917SN/A void process(); 1751917SN/A }; 1761917SN/A ProfileEvent *profileEvent; 1772SN/A#endif 1782SN/A 1792SN/A protected: 1802680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1814182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1822SN/A 1834776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1844776Sgblack@eecs.umich.edu 1852SN/A public: 186393SN/A 1877764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1887764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1897764Sgblack@eecs.umich.edu 1904776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1914776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1924776Sgblack@eecs.umich.edu 193393SN/A /// Notify the CPU that the indicated context is now active. The 194393SN/A /// delay parameter indicates the number of ticks to wait before 195393SN/A /// executing (typically 0 or 1). 196393SN/A virtual void activateContext(int thread_num, int delay) {} 197393SN/A 198393SN/A /// Notify the CPU that the indicated context is now suspended. 199393SN/A virtual void suspendContext(int thread_num) {} 200393SN/A 201393SN/A /// Notify the CPU that the indicated context is now deallocated. 202393SN/A virtual void deallocateContext(int thread_num) {} 203393SN/A 204393SN/A /// Notify the CPU that the indicated context is now halted. 205393SN/A virtual void haltContext(int thread_num) {} 2062SN/A 2074000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2084000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2094000Ssaidi@eecs.umich.edu 2104000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2114000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2124000Ssaidi@eecs.umich.edu 2132SN/A public: 2145529Snate@binkert.org typedef BaseCPUParams Params; 2155529Snate@binkert.org const Params *params() const 2165529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2171400SN/A BaseCPU(Params *params); 2181191SN/A virtual ~BaseCPU(); 2192SN/A 2201129SN/A virtual void init(); 2211917SN/A virtual void startup(); 2222SN/A virtual void regStats(); 2232SN/A 2246221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2252103SN/A 2262680Sktlim@umich.edu void registerThreadContexts(); 227180SN/A 2281492SN/A /// Prepare for another CPU to take over execution. When it is 2291492SN/A /// is ready (drained pipe) it signals the sampler. 2302798Sktlim@umich.edu virtual void switchOut(); 231180SN/A 232180SN/A /// Take over execution from the given CPU. Used for warm-up and 233180SN/A /// sampling. 2344192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 235180SN/A 236124SN/A /** 237124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 238124SN/A * This is a constant for the duration of the simulation. 239124SN/A */ 2406221Snate@binkert.org ThreadID numThreads; 2412SN/A 242124SN/A /** 243124SN/A * Vector of per-thread instruction-based event queues. Used for 244124SN/A * scheduling events based on number of instructions committed by 245124SN/A * a particular thread. 246124SN/A */ 247503SN/A EventQueue **comInstEventQueue; 2482SN/A 249124SN/A /** 250124SN/A * Vector of per-thread load-based event queues. Used for 251124SN/A * scheduling events based on number of loads committed by 252124SN/A *a particular thread. 253124SN/A */ 254124SN/A EventQueue **comLoadEventQueue; 255124SN/A 2562SN/A System *system; 257921SN/A 2583661Srdreslin@umich.edu Tick phase; 2593661Srdreslin@umich.edu 2602378SN/A#if FULL_SYSTEM 261921SN/A /** 262921SN/A * Serialize this object to the given output stream. 263921SN/A * @param os The stream to serialize to. 264921SN/A */ 265921SN/A virtual void serialize(std::ostream &os); 266921SN/A 267921SN/A /** 268921SN/A * Reconstruct the state of this object from a checkpoint. 269921SN/A * @param cp The checkpoint use. 270921SN/A * @param section The section name of this object 271921SN/A */ 272921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 273921SN/A 2742SN/A#endif 2752SN/A 276124SN/A /** 277124SN/A * Return pointer to CPU's branch predictor (NULL if none). 278124SN/A * @return Branch predictor pointer. 279124SN/A */ 2802SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2812SN/A 2826816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 283707SN/A 2841191SN/A // Function tracing 2851191SN/A private: 2861191SN/A bool functionTracingEnabled; 2871191SN/A std::ostream *functionTraceStream; 2881191SN/A Addr currentFunctionStart; 2891191SN/A Addr currentFunctionEnd; 2901191SN/A Tick functionEntryTick; 2911191SN/A void enableFunctionTrace(); 2921191SN/A void traceFunctionsInternal(Addr pc); 2931191SN/A 2941191SN/A protected: 2951191SN/A void traceFunctions(Addr pc) 2961191SN/A { 2971191SN/A if (functionTracingEnabled) 2981191SN/A traceFunctionsInternal(pc); 2991191SN/A } 3001191SN/A 3012SN/A private: 3022SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3032SN/A 3042SN/A public: 3052SN/A static int numSimulatedCPUs() { return cpuList.size(); } 306707SN/A static Counter numSimulatedInstructions() 307707SN/A { 308707SN/A Counter total = 0; 309707SN/A 310707SN/A int size = cpuList.size(); 311707SN/A for (int i = 0; i < size; ++i) 312707SN/A total += cpuList[i]->totalInstructions(); 313707SN/A 314707SN/A return total; 315707SN/A } 316707SN/A 317707SN/A public: 318707SN/A // Number of CPU cycles simulated 3195999Snate@binkert.org Stats::Scalar numCycles; 3207914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 3217914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 3222SN/A}; 3232SN/A 3241717SN/A#endif // __CPU_BASE_HH__ 325