base.hh revision 7764
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 385664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 39707SN/A#include "base/statistics.hh" 401858SN/A#include "config/full_system.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 4256SN/A#include "sim/eventq.hh" 434776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 442856Srdreslin@umich.edu#include "mem/mem_object.hh" 452SN/A 463520Sgblack@eecs.umich.edu#if FULL_SYSTEM 473520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 483520Sgblack@eecs.umich.edu#endif 493520Sgblack@eecs.umich.edu 505529Snate@binkert.orgclass BaseCPUParams; 512190SN/Aclass BranchPred; 522315SN/Aclass CheckerCPU; 532680Sktlim@umich.educlass ThreadContext; 542SN/Aclass System; 552856Srdreslin@umich.educlass Port; 562SN/A 574182Sgblack@eecs.umich.edunamespace TheISA 584182Sgblack@eecs.umich.edu{ 594182Sgblack@eecs.umich.edu class Predecoder; 604182Sgblack@eecs.umich.edu} 614182Sgblack@eecs.umich.edu 622356SN/Aclass CPUProgressEvent : public Event 632356SN/A{ 642356SN/A protected: 656144Sksewell@umich.edu Tick _interval; 662356SN/A Counter lastNumInst; 672356SN/A BaseCPU *cpu; 686144Sksewell@umich.edu bool _repeatEvent; 692356SN/A 702356SN/A public: 716144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 722356SN/A 732356SN/A void process(); 742356SN/A 756144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 766144Sksewell@umich.edu Tick interval() { return _interval; } 776144Sksewell@umich.edu 786144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 796144Sksewell@umich.edu 805336Shines@cs.fsu.edu virtual const char *description() const; 812356SN/A}; 822356SN/A 832856Srdreslin@umich.educlass BaseCPU : public MemObject 842SN/A{ 851634SN/A protected: 861634SN/A // CPU's clock period in terms of the number of ticks of curTime. 871695SN/A Tick clock; 883814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 893814Ssaidi@eecs.umich.edu Tick instCnt; 905712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 915712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 925715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 935712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 945712Shsul@eecs.umich.edu int _cpuId; 951634SN/A 961634SN/A public: 975712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 985712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 995712Shsul@eecs.umich.edu 1002359SN/A// Tick currentTick; 1017064Snate@binkert.org inline Tick frequency() const { return SimClock::Frequency / clock; } 1025100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1031695SN/A inline Tick curCycle() const { return curTick / clock; } 1045099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1053814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1063814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1071634SN/A 1083495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1093495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1103495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 1113495Sktlim@umich.edu */ 1123495Sktlim@umich.edu Tick nextCycle(); 1133495Sktlim@umich.edu 1143495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1153495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1163495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1173495Sktlim@umich.edu * current cycle. 1183495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1193495Sktlim@umich.edu */ 1203495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1213495Sktlim@umich.edu 1225664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1235664Sgblack@eecs.umich.edu 1241858SN/A#if FULL_SYSTEM 1252SN/A protected: 1265704Snate@binkert.org TheISA::Interrupts *interrupts; 1272SN/A 1282SN/A public: 1295645Sgblack@eecs.umich.edu TheISA::Interrupts * 1305645Sgblack@eecs.umich.edu getInterruptController() 1315645Sgblack@eecs.umich.edu { 1325647Sgblack@eecs.umich.edu return interrupts; 1335645Sgblack@eecs.umich.edu } 1345645Sgblack@eecs.umich.edu 1355807Snate@binkert.org virtual void wakeup() = 0; 1365807Snate@binkert.org 1375807Snate@binkert.org void 1385807Snate@binkert.org postInterrupt(int int_num, int index) 1395807Snate@binkert.org { 1405807Snate@binkert.org interrupts->post(int_num, index); 1415807Snate@binkert.org wakeup(); 1425807Snate@binkert.org } 1435807Snate@binkert.org 1445807Snate@binkert.org void 1455807Snate@binkert.org clearInterrupt(int int_num, int index) 1465807Snate@binkert.org { 1475807Snate@binkert.org interrupts->clear(int_num, index); 1485807Snate@binkert.org } 1495807Snate@binkert.org 1505807Snate@binkert.org void 1515807Snate@binkert.org clearInterrupts() 1525807Snate@binkert.org { 1535807Snate@binkert.org interrupts->clearAll(); 1545807Snate@binkert.org } 1552SN/A 1565704Snate@binkert.org bool 1575704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1585704Snate@binkert.org { 1595704Snate@binkert.org return interrupts->checkInterrupts(tc); 1605704Snate@binkert.org } 1611917SN/A 1621917SN/A class ProfileEvent : public Event 1631917SN/A { 1641917SN/A private: 1651917SN/A BaseCPU *cpu; 1665536Srstrong@hp.com Tick interval; 1671917SN/A 1681917SN/A public: 1695536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1701917SN/A void process(); 1711917SN/A }; 1721917SN/A ProfileEvent *profileEvent; 1732SN/A#endif 1742SN/A 1752SN/A protected: 1762680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1774182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1782SN/A 1794776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1804776Sgblack@eecs.umich.edu 1812SN/A public: 182393SN/A 1837764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 1847764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 1857764Sgblack@eecs.umich.edu 1864776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1874776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1884776Sgblack@eecs.umich.edu 189393SN/A /// Notify the CPU that the indicated context is now active. The 190393SN/A /// delay parameter indicates the number of ticks to wait before 191393SN/A /// executing (typically 0 or 1). 192393SN/A virtual void activateContext(int thread_num, int delay) {} 193393SN/A 194393SN/A /// Notify the CPU that the indicated context is now suspended. 195393SN/A virtual void suspendContext(int thread_num) {} 196393SN/A 197393SN/A /// Notify the CPU that the indicated context is now deallocated. 198393SN/A virtual void deallocateContext(int thread_num) {} 199393SN/A 200393SN/A /// Notify the CPU that the indicated context is now halted. 201393SN/A virtual void haltContext(int thread_num) {} 2022SN/A 2034000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2044000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2054000Ssaidi@eecs.umich.edu 2064000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2074000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2084000Ssaidi@eecs.umich.edu 2092SN/A public: 2105529Snate@binkert.org typedef BaseCPUParams Params; 2115529Snate@binkert.org const Params *params() const 2125529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2131400SN/A BaseCPU(Params *params); 2141191SN/A virtual ~BaseCPU(); 2152SN/A 2161129SN/A virtual void init(); 2171917SN/A virtual void startup(); 2182SN/A virtual void regStats(); 2192SN/A 2206221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2212103SN/A 2222680Sktlim@umich.edu void registerThreadContexts(); 223180SN/A 2241492SN/A /// Prepare for another CPU to take over execution. When it is 2251492SN/A /// is ready (drained pipe) it signals the sampler. 2262798Sktlim@umich.edu virtual void switchOut(); 227180SN/A 228180SN/A /// Take over execution from the given CPU. Used for warm-up and 229180SN/A /// sampling. 2304192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 231180SN/A 232124SN/A /** 233124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 234124SN/A * This is a constant for the duration of the simulation. 235124SN/A */ 2366221Snate@binkert.org ThreadID numThreads; 2372SN/A 2385529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2395529Snate@binkert.org 240124SN/A /** 241124SN/A * Vector of per-thread instruction-based event queues. Used for 242124SN/A * scheduling events based on number of instructions committed by 243124SN/A * a particular thread. 244124SN/A */ 245503SN/A EventQueue **comInstEventQueue; 2462SN/A 247124SN/A /** 248124SN/A * Vector of per-thread load-based event queues. Used for 249124SN/A * scheduling events based on number of loads committed by 250124SN/A *a particular thread. 251124SN/A */ 252124SN/A EventQueue **comLoadEventQueue; 253124SN/A 2542SN/A System *system; 255921SN/A 2563661Srdreslin@umich.edu Tick phase; 2573661Srdreslin@umich.edu 2582378SN/A#if FULL_SYSTEM 259921SN/A /** 260921SN/A * Serialize this object to the given output stream. 261921SN/A * @param os The stream to serialize to. 262921SN/A */ 263921SN/A virtual void serialize(std::ostream &os); 264921SN/A 265921SN/A /** 266921SN/A * Reconstruct the state of this object from a checkpoint. 267921SN/A * @param cp The checkpoint use. 268921SN/A * @param section The section name of this object 269921SN/A */ 270921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 271921SN/A 2722SN/A#endif 2732SN/A 274124SN/A /** 275124SN/A * Return pointer to CPU's branch predictor (NULL if none). 276124SN/A * @return Branch predictor pointer. 277124SN/A */ 2782SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2792SN/A 2806816SLisa.Hsu@amd.com virtual Counter totalInstructions() const = 0; 281707SN/A 2821191SN/A // Function tracing 2831191SN/A private: 2841191SN/A bool functionTracingEnabled; 2851191SN/A std::ostream *functionTraceStream; 2861191SN/A Addr currentFunctionStart; 2871191SN/A Addr currentFunctionEnd; 2881191SN/A Tick functionEntryTick; 2891191SN/A void enableFunctionTrace(); 2901191SN/A void traceFunctionsInternal(Addr pc); 2911191SN/A 2921191SN/A protected: 2931191SN/A void traceFunctions(Addr pc) 2941191SN/A { 2951191SN/A if (functionTracingEnabled) 2961191SN/A traceFunctionsInternal(pc); 2971191SN/A } 2981191SN/A 2992SN/A private: 3002SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3012SN/A 3022SN/A public: 3032SN/A static int numSimulatedCPUs() { return cpuList.size(); } 304707SN/A static Counter numSimulatedInstructions() 305707SN/A { 306707SN/A Counter total = 0; 307707SN/A 308707SN/A int size = cpuList.size(); 309707SN/A for (int i = 0; i < size; ++i) 310707SN/A total += cpuList[i]->totalInstructions(); 311707SN/A 312707SN/A return total; 313707SN/A } 314707SN/A 315707SN/A public: 316707SN/A // Number of CPU cycles simulated 3175999Snate@binkert.org Stats::Scalar numCycles; 3182SN/A}; 3192SN/A 3201717SN/A#endif // __CPU_BASE_HH__ 321