base.hh revision 6144
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 385664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 39707SN/A#include "base/statistics.hh" 401858SN/A#include "config/full_system.hh" 4156SN/A#include "sim/eventq.hh" 424776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 432856Srdreslin@umich.edu#include "mem/mem_object.hh" 442SN/A 453520Sgblack@eecs.umich.edu#if FULL_SYSTEM 463520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 473520Sgblack@eecs.umich.edu#endif 483520Sgblack@eecs.umich.edu 495529Snate@binkert.orgclass BaseCPUParams; 502190SN/Aclass BranchPred; 512315SN/Aclass CheckerCPU; 522680Sktlim@umich.educlass ThreadContext; 532SN/Aclass System; 542856Srdreslin@umich.educlass Port; 552SN/A 564182Sgblack@eecs.umich.edunamespace TheISA 574182Sgblack@eecs.umich.edu{ 584182Sgblack@eecs.umich.edu class Predecoder; 594182Sgblack@eecs.umich.edu} 604182Sgblack@eecs.umich.edu 612356SN/Aclass CPUProgressEvent : public Event 622356SN/A{ 632356SN/A protected: 646144Sksewell@umich.edu Tick _interval; 652356SN/A Counter lastNumInst; 662356SN/A BaseCPU *cpu; 676144Sksewell@umich.edu bool _repeatEvent; 682356SN/A 692356SN/A public: 706144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 712356SN/A 722356SN/A void process(); 732356SN/A 746144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 756144Sksewell@umich.edu Tick interval() { return _interval; } 766144Sksewell@umich.edu 776144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 786144Sksewell@umich.edu 795336Shines@cs.fsu.edu virtual const char *description() const; 802356SN/A}; 812356SN/A 822856Srdreslin@umich.educlass BaseCPU : public MemObject 832SN/A{ 841634SN/A protected: 851634SN/A // CPU's clock period in terms of the number of ticks of curTime. 861695SN/A Tick clock; 873814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 883814Ssaidi@eecs.umich.edu Tick instCnt; 895712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 905712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 915715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 925712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 935712Shsul@eecs.umich.edu int _cpuId; 941634SN/A 951634SN/A public: 965712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 975712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 985712Shsul@eecs.umich.edu 992359SN/A// Tick currentTick; 1001695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 1015100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 1021695SN/A inline Tick curCycle() const { return curTick / clock; } 1035099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 1043814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1053814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1061634SN/A 1073495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1083495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1093495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 1103495Sktlim@umich.edu */ 1113495Sktlim@umich.edu Tick nextCycle(); 1123495Sktlim@umich.edu 1133495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1143495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1153495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1163495Sktlim@umich.edu * current cycle. 1173495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1183495Sktlim@umich.edu */ 1193495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1203495Sktlim@umich.edu 1215664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1225664Sgblack@eecs.umich.edu 1231858SN/A#if FULL_SYSTEM 1242SN/A protected: 1255704Snate@binkert.org TheISA::Interrupts *interrupts; 1262SN/A 1272SN/A public: 1285645Sgblack@eecs.umich.edu TheISA::Interrupts * 1295645Sgblack@eecs.umich.edu getInterruptController() 1305645Sgblack@eecs.umich.edu { 1315647Sgblack@eecs.umich.edu return interrupts; 1325645Sgblack@eecs.umich.edu } 1335645Sgblack@eecs.umich.edu 1345807Snate@binkert.org virtual void wakeup() = 0; 1355807Snate@binkert.org 1365807Snate@binkert.org void 1375807Snate@binkert.org postInterrupt(int int_num, int index) 1385807Snate@binkert.org { 1395807Snate@binkert.org interrupts->post(int_num, index); 1405807Snate@binkert.org wakeup(); 1415807Snate@binkert.org } 1425807Snate@binkert.org 1435807Snate@binkert.org void 1445807Snate@binkert.org clearInterrupt(int int_num, int index) 1455807Snate@binkert.org { 1465807Snate@binkert.org interrupts->clear(int_num, index); 1475807Snate@binkert.org } 1485807Snate@binkert.org 1495807Snate@binkert.org void 1505807Snate@binkert.org clearInterrupts() 1515807Snate@binkert.org { 1525807Snate@binkert.org interrupts->clearAll(); 1535807Snate@binkert.org } 1542SN/A 1555704Snate@binkert.org bool 1565704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1575704Snate@binkert.org { 1585704Snate@binkert.org return interrupts->checkInterrupts(tc); 1595704Snate@binkert.org } 1601917SN/A 1611917SN/A class ProfileEvent : public Event 1621917SN/A { 1631917SN/A private: 1641917SN/A BaseCPU *cpu; 1655536Srstrong@hp.com Tick interval; 1661917SN/A 1671917SN/A public: 1685536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1691917SN/A void process(); 1701917SN/A }; 1711917SN/A ProfileEvent *profileEvent; 1722SN/A#endif 1732SN/A 1742SN/A protected: 1752680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1764182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1772SN/A 1784776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1794776Sgblack@eecs.umich.edu 1802SN/A public: 181393SN/A 1824776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1834776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1844776Sgblack@eecs.umich.edu 185393SN/A /// Notify the CPU that the indicated context is now active. The 186393SN/A /// delay parameter indicates the number of ticks to wait before 187393SN/A /// executing (typically 0 or 1). 188393SN/A virtual void activateContext(int thread_num, int delay) {} 189393SN/A 190393SN/A /// Notify the CPU that the indicated context is now suspended. 191393SN/A virtual void suspendContext(int thread_num) {} 192393SN/A 193393SN/A /// Notify the CPU that the indicated context is now deallocated. 194393SN/A virtual void deallocateContext(int thread_num) {} 195393SN/A 196393SN/A /// Notify the CPU that the indicated context is now halted. 197393SN/A virtual void haltContext(int thread_num) {} 1982SN/A 1994000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2004000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2014000Ssaidi@eecs.umich.edu 2024000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2034000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2044000Ssaidi@eecs.umich.edu 2052SN/A public: 2065529Snate@binkert.org typedef BaseCPUParams Params; 2075529Snate@binkert.org const Params *params() const 2085529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2091400SN/A BaseCPU(Params *params); 2101191SN/A virtual ~BaseCPU(); 2112SN/A 2121129SN/A virtual void init(); 2131917SN/A virtual void startup(); 2142SN/A virtual void regStats(); 2152SN/A 2162103SN/A virtual void activateWhenReady(int tid) {}; 2172103SN/A 2182680Sktlim@umich.edu void registerThreadContexts(); 219180SN/A 2201492SN/A /// Prepare for another CPU to take over execution. When it is 2211492SN/A /// is ready (drained pipe) it signals the sampler. 2222798Sktlim@umich.edu virtual void switchOut(); 223180SN/A 224180SN/A /// Take over execution from the given CPU. Used for warm-up and 225180SN/A /// sampling. 2264192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 227180SN/A 228124SN/A /** 229124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 230124SN/A * This is a constant for the duration of the simulation. 231124SN/A */ 2322SN/A int number_of_threads; 2332SN/A 2345529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2355529Snate@binkert.org 236124SN/A /** 237124SN/A * Vector of per-thread instruction-based event queues. Used for 238124SN/A * scheduling events based on number of instructions committed by 239124SN/A * a particular thread. 240124SN/A */ 241503SN/A EventQueue **comInstEventQueue; 2422SN/A 243124SN/A /** 244124SN/A * Vector of per-thread load-based event queues. Used for 245124SN/A * scheduling events based on number of loads committed by 246124SN/A *a particular thread. 247124SN/A */ 248124SN/A EventQueue **comLoadEventQueue; 249124SN/A 2502SN/A System *system; 251921SN/A 2523661Srdreslin@umich.edu Tick phase; 2533661Srdreslin@umich.edu 2542378SN/A#if FULL_SYSTEM 255921SN/A /** 256921SN/A * Serialize this object to the given output stream. 257921SN/A * @param os The stream to serialize to. 258921SN/A */ 259921SN/A virtual void serialize(std::ostream &os); 260921SN/A 261921SN/A /** 262921SN/A * Reconstruct the state of this object from a checkpoint. 263921SN/A * @param cp The checkpoint use. 264921SN/A * @param section The section name of this object 265921SN/A */ 266921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 267921SN/A 2682SN/A#endif 2692SN/A 270124SN/A /** 271124SN/A * Return pointer to CPU's branch predictor (NULL if none). 272124SN/A * @return Branch predictor pointer. 273124SN/A */ 2742SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2752SN/A 276707SN/A virtual Counter totalInstructions() const { return 0; } 277707SN/A 2781191SN/A // Function tracing 2791191SN/A private: 2801191SN/A bool functionTracingEnabled; 2811191SN/A std::ostream *functionTraceStream; 2821191SN/A Addr currentFunctionStart; 2831191SN/A Addr currentFunctionEnd; 2841191SN/A Tick functionEntryTick; 2851191SN/A void enableFunctionTrace(); 2861191SN/A void traceFunctionsInternal(Addr pc); 2871191SN/A 2881191SN/A protected: 2891191SN/A void traceFunctions(Addr pc) 2901191SN/A { 2911191SN/A if (functionTracingEnabled) 2921191SN/A traceFunctionsInternal(pc); 2931191SN/A } 2941191SN/A 2952SN/A private: 2962SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2972SN/A 2982SN/A public: 2992SN/A static int numSimulatedCPUs() { return cpuList.size(); } 300707SN/A static Counter numSimulatedInstructions() 301707SN/A { 302707SN/A Counter total = 0; 303707SN/A 304707SN/A int size = cpuList.size(); 305707SN/A for (int i = 0; i < size; ++i) 306707SN/A total += cpuList[i]->totalInstructions(); 307707SN/A 308707SN/A return total; 309707SN/A } 310707SN/A 311707SN/A public: 312707SN/A // Number of CPU cycles simulated 3135999Snate@binkert.org Stats::Scalar numCycles; 3142SN/A}; 3152SN/A 3161717SN/A#endif // __CPU_BASE_HH__ 317