base.hh revision 6122
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 385664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 39707SN/A#include "base/statistics.hh" 401858SN/A#include "config/full_system.hh" 4156SN/A#include "sim/eventq.hh" 424776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 432856Srdreslin@umich.edu#include "mem/mem_object.hh" 442SN/A 453520Sgblack@eecs.umich.edu#if FULL_SYSTEM 463520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 473520Sgblack@eecs.umich.edu#endif 483520Sgblack@eecs.umich.edu 495529Snate@binkert.orgclass BaseCPUParams; 502190SN/Aclass BranchPred; 512315SN/Aclass CheckerCPU; 522680Sktlim@umich.educlass ThreadContext; 532SN/Aclass System; 542856Srdreslin@umich.educlass Port; 552SN/A 564182Sgblack@eecs.umich.edunamespace TheISA 574182Sgblack@eecs.umich.edu{ 584182Sgblack@eecs.umich.edu class Predecoder; 594182Sgblack@eecs.umich.edu} 604182Sgblack@eecs.umich.edu 612356SN/Aclass CPUProgressEvent : public Event 622356SN/A{ 632356SN/A protected: 642356SN/A Tick interval; 652356SN/A Counter lastNumInst; 662356SN/A BaseCPU *cpu; 672356SN/A 682356SN/A public: 695606Snate@binkert.org CPUProgressEvent(BaseCPU *_cpu, Tick ival); 702356SN/A 712356SN/A void process(); 722356SN/A 735336Shines@cs.fsu.edu virtual const char *description() const; 742356SN/A}; 752356SN/A 762856Srdreslin@umich.educlass BaseCPU : public MemObject 772SN/A{ 781634SN/A protected: 791634SN/A // CPU's clock period in terms of the number of ticks of curTime. 801695SN/A Tick clock; 813814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 823814Ssaidi@eecs.umich.edu Tick instCnt; 835712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 845712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 855715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 865712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 875712Shsul@eecs.umich.edu int _cpuId; 881634SN/A 891634SN/A public: 905712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 915712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 925712Shsul@eecs.umich.edu 932359SN/A// Tick currentTick; 941695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 955100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 961695SN/A inline Tick curCycle() const { return curTick / clock; } 975099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 983814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 993814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1001634SN/A 1013495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1023495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1033495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 1043495Sktlim@umich.edu */ 1053495Sktlim@umich.edu Tick nextCycle(); 1063495Sktlim@umich.edu 1073495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1083495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1093495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1103495Sktlim@umich.edu * current cycle. 1113495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1123495Sktlim@umich.edu */ 1133495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1143495Sktlim@umich.edu 1155664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1165664Sgblack@eecs.umich.edu 1171858SN/A#if FULL_SYSTEM 1182SN/A protected: 1195704Snate@binkert.org TheISA::Interrupts *interrupts; 1202SN/A 1212SN/A public: 1225645Sgblack@eecs.umich.edu TheISA::Interrupts * 1235645Sgblack@eecs.umich.edu getInterruptController() 1245645Sgblack@eecs.umich.edu { 1255647Sgblack@eecs.umich.edu return interrupts; 1265645Sgblack@eecs.umich.edu } 1275645Sgblack@eecs.umich.edu 1285807Snate@binkert.org virtual void wakeup() = 0; 1295807Snate@binkert.org 1305807Snate@binkert.org void 1315807Snate@binkert.org postInterrupt(int int_num, int index) 1325807Snate@binkert.org { 1335807Snate@binkert.org interrupts->post(int_num, index); 1345807Snate@binkert.org wakeup(); 1355807Snate@binkert.org } 1365807Snate@binkert.org 1375807Snate@binkert.org void 1385807Snate@binkert.org clearInterrupt(int int_num, int index) 1395807Snate@binkert.org { 1405807Snate@binkert.org interrupts->clear(int_num, index); 1415807Snate@binkert.org } 1425807Snate@binkert.org 1435807Snate@binkert.org void 1445807Snate@binkert.org clearInterrupts() 1455807Snate@binkert.org { 1465807Snate@binkert.org interrupts->clearAll(); 1475807Snate@binkert.org } 1482SN/A 1495704Snate@binkert.org bool 1505704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1515704Snate@binkert.org { 1525704Snate@binkert.org return interrupts->checkInterrupts(tc); 1535704Snate@binkert.org } 1541917SN/A 1551917SN/A class ProfileEvent : public Event 1561917SN/A { 1571917SN/A private: 1581917SN/A BaseCPU *cpu; 1595536Srstrong@hp.com Tick interval; 1601917SN/A 1611917SN/A public: 1625536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1631917SN/A void process(); 1641917SN/A }; 1651917SN/A ProfileEvent *profileEvent; 1662SN/A#endif 1672SN/A 1682SN/A protected: 1692680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1704182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1712SN/A 1724776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1734776Sgblack@eecs.umich.edu 1742SN/A public: 175393SN/A 1764776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1774776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1784776Sgblack@eecs.umich.edu 179393SN/A /// Notify the CPU that the indicated context is now active. The 180393SN/A /// delay parameter indicates the number of ticks to wait before 181393SN/A /// executing (typically 0 or 1). 182393SN/A virtual void activateContext(int thread_num, int delay) {} 183393SN/A 184393SN/A /// Notify the CPU that the indicated context is now suspended. 185393SN/A virtual void suspendContext(int thread_num) {} 186393SN/A 187393SN/A /// Notify the CPU that the indicated context is now deallocated. 188393SN/A virtual void deallocateContext(int thread_num) {} 189393SN/A 190393SN/A /// Notify the CPU that the indicated context is now halted. 191393SN/A virtual void haltContext(int thread_num) {} 1922SN/A 1934000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1944000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1954000Ssaidi@eecs.umich.edu 1964000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1974000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1984000Ssaidi@eecs.umich.edu 1992SN/A public: 2005529Snate@binkert.org typedef BaseCPUParams Params; 2015529Snate@binkert.org const Params *params() const 2025529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2031400SN/A BaseCPU(Params *params); 2041191SN/A virtual ~BaseCPU(); 2052SN/A 2061129SN/A virtual void init(); 2071917SN/A virtual void startup(); 2082SN/A virtual void regStats(); 2092SN/A 2102103SN/A virtual void activateWhenReady(int tid) {}; 2112103SN/A 2122680Sktlim@umich.edu void registerThreadContexts(); 213180SN/A 2141492SN/A /// Prepare for another CPU to take over execution. When it is 2151492SN/A /// is ready (drained pipe) it signals the sampler. 2162798Sktlim@umich.edu virtual void switchOut(); 217180SN/A 218180SN/A /// Take over execution from the given CPU. Used for warm-up and 219180SN/A /// sampling. 2204192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 221180SN/A 222124SN/A /** 223124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 224124SN/A * This is a constant for the duration of the simulation. 225124SN/A */ 2262SN/A int number_of_threads; 2272SN/A 2285529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2295529Snate@binkert.org 230124SN/A /** 231124SN/A * Vector of per-thread instruction-based event queues. Used for 232124SN/A * scheduling events based on number of instructions committed by 233124SN/A * a particular thread. 234124SN/A */ 235503SN/A EventQueue **comInstEventQueue; 2362SN/A 237124SN/A /** 238124SN/A * Vector of per-thread load-based event queues. Used for 239124SN/A * scheduling events based on number of loads committed by 240124SN/A *a particular thread. 241124SN/A */ 242124SN/A EventQueue **comLoadEventQueue; 243124SN/A 2442SN/A System *system; 245921SN/A 2463661Srdreslin@umich.edu Tick phase; 2473661Srdreslin@umich.edu 2482378SN/A#if FULL_SYSTEM 249921SN/A /** 250921SN/A * Serialize this object to the given output stream. 251921SN/A * @param os The stream to serialize to. 252921SN/A */ 253921SN/A virtual void serialize(std::ostream &os); 254921SN/A 255921SN/A /** 256921SN/A * Reconstruct the state of this object from a checkpoint. 257921SN/A * @param cp The checkpoint use. 258921SN/A * @param section The section name of this object 259921SN/A */ 260921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 261921SN/A 2622SN/A#endif 2632SN/A 264124SN/A /** 265124SN/A * Return pointer to CPU's branch predictor (NULL if none). 266124SN/A * @return Branch predictor pointer. 267124SN/A */ 2682SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2692SN/A 270707SN/A virtual Counter totalInstructions() const { return 0; } 271707SN/A 2721191SN/A // Function tracing 2731191SN/A private: 2741191SN/A bool functionTracingEnabled; 2751191SN/A std::ostream *functionTraceStream; 2761191SN/A Addr currentFunctionStart; 2771191SN/A Addr currentFunctionEnd; 2781191SN/A Tick functionEntryTick; 2791191SN/A void enableFunctionTrace(); 2801191SN/A void traceFunctionsInternal(Addr pc); 2811191SN/A 2821191SN/A protected: 2831191SN/A void traceFunctions(Addr pc) 2841191SN/A { 2851191SN/A if (functionTracingEnabled) 2861191SN/A traceFunctionsInternal(pc); 2871191SN/A } 2881191SN/A 2892SN/A private: 2902SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2912SN/A 2922SN/A public: 2932SN/A static int numSimulatedCPUs() { return cpuList.size(); } 294707SN/A static Counter numSimulatedInstructions() 295707SN/A { 296707SN/A Counter total = 0; 297707SN/A 298707SN/A int size = cpuList.size(); 299707SN/A for (int i = 0; i < size; ++i) 300707SN/A total += cpuList[i]->totalInstructions(); 301707SN/A 302707SN/A return total; 303707SN/A } 304707SN/A 305707SN/A public: 306707SN/A // Number of CPU cycles simulated 3075999Snate@binkert.org Stats::Scalar numCycles; 3082SN/A}; 3092SN/A 3101717SN/A#endif // __CPU_BASE_HH__ 311