base.hh revision 5715
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 385664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 39707SN/A#include "base/statistics.hh" 401858SN/A#include "config/full_system.hh" 4156SN/A#include "sim/eventq.hh" 424776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 432856Srdreslin@umich.edu#include "mem/mem_object.hh" 442SN/A 453520Sgblack@eecs.umich.edu#if FULL_SYSTEM 463520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 473520Sgblack@eecs.umich.edu#endif 483520Sgblack@eecs.umich.edu 495529Snate@binkert.orgclass BaseCPUParams; 502190SN/Aclass BranchPred; 512315SN/Aclass CheckerCPU; 522680Sktlim@umich.educlass ThreadContext; 532SN/Aclass System; 542856Srdreslin@umich.educlass Port; 552SN/A 564182Sgblack@eecs.umich.edunamespace TheISA 574182Sgblack@eecs.umich.edu{ 584182Sgblack@eecs.umich.edu class Predecoder; 594182Sgblack@eecs.umich.edu} 604182Sgblack@eecs.umich.edu 612356SN/Aclass CPUProgressEvent : public Event 622356SN/A{ 632356SN/A protected: 642356SN/A Tick interval; 652356SN/A Counter lastNumInst; 662356SN/A BaseCPU *cpu; 672356SN/A 682356SN/A public: 695606Snate@binkert.org CPUProgressEvent(BaseCPU *_cpu, Tick ival); 702356SN/A 712356SN/A void process(); 722356SN/A 735336Shines@cs.fsu.edu virtual const char *description() const; 742356SN/A}; 752356SN/A 762856Srdreslin@umich.educlass BaseCPU : public MemObject 772SN/A{ 781634SN/A protected: 791634SN/A // CPU's clock period in terms of the number of ticks of curTime. 801695SN/A Tick clock; 813814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 823814Ssaidi@eecs.umich.edu Tick instCnt; 835712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 845712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 855715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 865712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 875712Shsul@eecs.umich.edu int _cpuId; 881634SN/A 891634SN/A public: 905712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 915712Shsul@eecs.umich.edu int cpuId() { return _cpuId; } 925712Shsul@eecs.umich.edu 932359SN/A// Tick currentTick; 941695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 955100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 961695SN/A inline Tick curCycle() const { return curTick / clock; } 975099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 983814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 993814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1001634SN/A 1013495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1023495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 1033495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 1043495Sktlim@umich.edu */ 1053495Sktlim@umich.edu Tick nextCycle(); 1063495Sktlim@umich.edu 1073495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1083495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1093495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1103495Sktlim@umich.edu * current cycle. 1113495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1123495Sktlim@umich.edu */ 1133495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1143495Sktlim@umich.edu 1155664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1165664Sgblack@eecs.umich.edu 1171858SN/A#if FULL_SYSTEM 1182SN/A protected: 1195704Snate@binkert.org TheISA::Interrupts *interrupts; 1202SN/A 1212SN/A public: 1225645Sgblack@eecs.umich.edu TheISA::Interrupts * 1235645Sgblack@eecs.umich.edu getInterruptController() 1245645Sgblack@eecs.umich.edu { 1255647Sgblack@eecs.umich.edu return interrupts; 1265645Sgblack@eecs.umich.edu } 1275645Sgblack@eecs.umich.edu 1285704Snate@binkert.org virtual void postInterrupt(int int_num, int index); 1295704Snate@binkert.org virtual void clearInterrupt(int int_num, int index); 1305704Snate@binkert.org virtual void clearInterrupts(); 1312SN/A 1325704Snate@binkert.org bool 1335704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1345704Snate@binkert.org { 1355704Snate@binkert.org return interrupts->checkInterrupts(tc); 1365704Snate@binkert.org } 1371917SN/A 1381917SN/A class ProfileEvent : public Event 1391917SN/A { 1401917SN/A private: 1411917SN/A BaseCPU *cpu; 1425536Srstrong@hp.com Tick interval; 1431917SN/A 1441917SN/A public: 1455536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1461917SN/A void process(); 1471917SN/A }; 1481917SN/A ProfileEvent *profileEvent; 1492SN/A#endif 1502SN/A 1512SN/A protected: 1522680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1534182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1542SN/A 1554776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1564776Sgblack@eecs.umich.edu 1572SN/A public: 158393SN/A 1594776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1604776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1614776Sgblack@eecs.umich.edu 162393SN/A /// Notify the CPU that the indicated context is now active. The 163393SN/A /// delay parameter indicates the number of ticks to wait before 164393SN/A /// executing (typically 0 or 1). 165393SN/A virtual void activateContext(int thread_num, int delay) {} 166393SN/A 167393SN/A /// Notify the CPU that the indicated context is now suspended. 168393SN/A virtual void suspendContext(int thread_num) {} 169393SN/A 170393SN/A /// Notify the CPU that the indicated context is now deallocated. 171393SN/A virtual void deallocateContext(int thread_num) {} 172393SN/A 173393SN/A /// Notify the CPU that the indicated context is now halted. 174393SN/A virtual void haltContext(int thread_num) {} 1752SN/A 1764000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1774000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1784000Ssaidi@eecs.umich.edu 1794000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1804000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1814000Ssaidi@eecs.umich.edu 1822SN/A public: 1835529Snate@binkert.org typedef BaseCPUParams Params; 1845529Snate@binkert.org const Params *params() const 1855529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 1861400SN/A BaseCPU(Params *params); 1871191SN/A virtual ~BaseCPU(); 1882SN/A 1891129SN/A virtual void init(); 1901917SN/A virtual void startup(); 1912SN/A virtual void regStats(); 1922SN/A 1932103SN/A virtual void activateWhenReady(int tid) {}; 1942103SN/A 1952680Sktlim@umich.edu void registerThreadContexts(); 196180SN/A 1971492SN/A /// Prepare for another CPU to take over execution. When it is 1981492SN/A /// is ready (drained pipe) it signals the sampler. 1992798Sktlim@umich.edu virtual void switchOut(); 200180SN/A 201180SN/A /// Take over execution from the given CPU. Used for warm-up and 202180SN/A /// sampling. 2034192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 204180SN/A 205124SN/A /** 206124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 207124SN/A * This is a constant for the duration of the simulation. 208124SN/A */ 2092SN/A int number_of_threads; 2102SN/A 2115529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2125529Snate@binkert.org 213124SN/A /** 214124SN/A * Vector of per-thread instruction-based event queues. Used for 215124SN/A * scheduling events based on number of instructions committed by 216124SN/A * a particular thread. 217124SN/A */ 218503SN/A EventQueue **comInstEventQueue; 2192SN/A 220124SN/A /** 221124SN/A * Vector of per-thread load-based event queues. Used for 222124SN/A * scheduling events based on number of loads committed by 223124SN/A *a particular thread. 224124SN/A */ 225124SN/A EventQueue **comLoadEventQueue; 226124SN/A 2272SN/A System *system; 228921SN/A 2293661Srdreslin@umich.edu Tick phase; 2303661Srdreslin@umich.edu 2312378SN/A#if FULL_SYSTEM 232921SN/A /** 233921SN/A * Serialize this object to the given output stream. 234921SN/A * @param os The stream to serialize to. 235921SN/A */ 236921SN/A virtual void serialize(std::ostream &os); 237921SN/A 238921SN/A /** 239921SN/A * Reconstruct the state of this object from a checkpoint. 240921SN/A * @param cp The checkpoint use. 241921SN/A * @param section The section name of this object 242921SN/A */ 243921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 244921SN/A 2452SN/A#endif 2462SN/A 247124SN/A /** 248124SN/A * Return pointer to CPU's branch predictor (NULL if none). 249124SN/A * @return Branch predictor pointer. 250124SN/A */ 2512SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2522SN/A 253707SN/A virtual Counter totalInstructions() const { return 0; } 254707SN/A 2551191SN/A // Function tracing 2561191SN/A private: 2571191SN/A bool functionTracingEnabled; 2581191SN/A std::ostream *functionTraceStream; 2591191SN/A Addr currentFunctionStart; 2601191SN/A Addr currentFunctionEnd; 2611191SN/A Tick functionEntryTick; 2621191SN/A void enableFunctionTrace(); 2631191SN/A void traceFunctionsInternal(Addr pc); 2641191SN/A 2651191SN/A protected: 2661191SN/A void traceFunctions(Addr pc) 2671191SN/A { 2681191SN/A if (functionTracingEnabled) 2691191SN/A traceFunctionsInternal(pc); 2701191SN/A } 2711191SN/A 2722SN/A private: 2732SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2742SN/A 2752SN/A public: 2762SN/A static int numSimulatedCPUs() { return cpuList.size(); } 277707SN/A static Counter numSimulatedInstructions() 278707SN/A { 279707SN/A Counter total = 0; 280707SN/A 281707SN/A int size = cpuList.size(); 282707SN/A for (int i = 0; i < size; ++i) 283707SN/A total += cpuList[i]->totalInstructions(); 284707SN/A 285707SN/A return total; 286707SN/A } 287707SN/A 288707SN/A public: 289707SN/A // Number of CPU cycles simulated 290729SN/A Stats::Scalar<> numCycles; 2912SN/A}; 2922SN/A 2931717SN/A#endif // __CPU_BASE_HH__ 294