base.hh revision 5704
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 385664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 39707SN/A#include "base/statistics.hh" 401858SN/A#include "config/full_system.hh" 4156SN/A#include "sim/eventq.hh" 424776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 432856Srdreslin@umich.edu#include "mem/mem_object.hh" 442SN/A 453520Sgblack@eecs.umich.edu#if FULL_SYSTEM 463520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 473520Sgblack@eecs.umich.edu#endif 483520Sgblack@eecs.umich.edu 495529Snate@binkert.orgclass BaseCPUParams; 502190SN/Aclass BranchPred; 512315SN/Aclass CheckerCPU; 522680Sktlim@umich.educlass ThreadContext; 532SN/Aclass System; 542856Srdreslin@umich.educlass Port; 552SN/A 564182Sgblack@eecs.umich.edunamespace TheISA 574182Sgblack@eecs.umich.edu{ 584182Sgblack@eecs.umich.edu class Predecoder; 594182Sgblack@eecs.umich.edu} 604182Sgblack@eecs.umich.edu 612356SN/Aclass CPUProgressEvent : public Event 622356SN/A{ 632356SN/A protected: 642356SN/A Tick interval; 652356SN/A Counter lastNumInst; 662356SN/A BaseCPU *cpu; 672356SN/A 682356SN/A public: 695606Snate@binkert.org CPUProgressEvent(BaseCPU *_cpu, Tick ival); 702356SN/A 712356SN/A void process(); 722356SN/A 735336Shines@cs.fsu.edu virtual const char *description() const; 742356SN/A}; 752356SN/A 762856Srdreslin@umich.educlass BaseCPU : public MemObject 772SN/A{ 781634SN/A protected: 791634SN/A // CPU's clock period in terms of the number of ticks of curTime. 801695SN/A Tick clock; 813814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 823814Ssaidi@eecs.umich.edu Tick instCnt; 831634SN/A 841634SN/A public: 852359SN/A// Tick currentTick; 861695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 875100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 881695SN/A inline Tick curCycle() const { return curTick / clock; } 895099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 903814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 913814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 921634SN/A 933495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 943495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 953495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 963495Sktlim@umich.edu */ 973495Sktlim@umich.edu Tick nextCycle(); 983495Sktlim@umich.edu 993495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 1003495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1013495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1023495Sktlim@umich.edu * current cycle. 1033495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1043495Sktlim@umich.edu */ 1053495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1063495Sktlim@umich.edu 1075664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1085664Sgblack@eecs.umich.edu 1091858SN/A#if FULL_SYSTEM 1102SN/A protected: 1115704Snate@binkert.org TheISA::Interrupts *interrupts; 1122SN/A 1132SN/A public: 1145645Sgblack@eecs.umich.edu TheISA::Interrupts * 1155645Sgblack@eecs.umich.edu getInterruptController() 1165645Sgblack@eecs.umich.edu { 1175647Sgblack@eecs.umich.edu return interrupts; 1185645Sgblack@eecs.umich.edu } 1195645Sgblack@eecs.umich.edu 1205704Snate@binkert.org virtual void postInterrupt(int int_num, int index); 1215704Snate@binkert.org virtual void clearInterrupt(int int_num, int index); 1225704Snate@binkert.org virtual void clearInterrupts(); 1232SN/A 1245704Snate@binkert.org bool 1255704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1265704Snate@binkert.org { 1275704Snate@binkert.org return interrupts->checkInterrupts(tc); 1285704Snate@binkert.org } 1291917SN/A 1301917SN/A class ProfileEvent : public Event 1311917SN/A { 1321917SN/A private: 1331917SN/A BaseCPU *cpu; 1345536Srstrong@hp.com Tick interval; 1351917SN/A 1361917SN/A public: 1375536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1381917SN/A void process(); 1391917SN/A }; 1401917SN/A ProfileEvent *profileEvent; 1412SN/A#endif 1422SN/A 1432SN/A protected: 1442680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1454182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1462SN/A 1474776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1484776Sgblack@eecs.umich.edu 1492SN/A public: 150393SN/A 1514776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1524776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1534776Sgblack@eecs.umich.edu 154393SN/A /// Notify the CPU that the indicated context is now active. The 155393SN/A /// delay parameter indicates the number of ticks to wait before 156393SN/A /// executing (typically 0 or 1). 157393SN/A virtual void activateContext(int thread_num, int delay) {} 158393SN/A 159393SN/A /// Notify the CPU that the indicated context is now suspended. 160393SN/A virtual void suspendContext(int thread_num) {} 161393SN/A 162393SN/A /// Notify the CPU that the indicated context is now deallocated. 163393SN/A virtual void deallocateContext(int thread_num) {} 164393SN/A 165393SN/A /// Notify the CPU that the indicated context is now halted. 166393SN/A virtual void haltContext(int thread_num) {} 1672SN/A 1684000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1694000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1704000Ssaidi@eecs.umich.edu 1714000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1724000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1734000Ssaidi@eecs.umich.edu 1742SN/A public: 1755529Snate@binkert.org typedef BaseCPUParams Params; 1765529Snate@binkert.org const Params *params() const 1775529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 1781400SN/A BaseCPU(Params *params); 1791191SN/A virtual ~BaseCPU(); 1802SN/A 1811129SN/A virtual void init(); 1821917SN/A virtual void startup(); 1832SN/A virtual void regStats(); 1842SN/A 1852103SN/A virtual void activateWhenReady(int tid) {}; 1862103SN/A 1872680Sktlim@umich.edu void registerThreadContexts(); 188180SN/A 1891492SN/A /// Prepare for another CPU to take over execution. When it is 1901492SN/A /// is ready (drained pipe) it signals the sampler. 1912798Sktlim@umich.edu virtual void switchOut(); 192180SN/A 193180SN/A /// Take over execution from the given CPU. Used for warm-up and 194180SN/A /// sampling. 1954192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 196180SN/A 197124SN/A /** 198124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 199124SN/A * This is a constant for the duration of the simulation. 200124SN/A */ 2012SN/A int number_of_threads; 2022SN/A 2035529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2045529Snate@binkert.org 205124SN/A /** 206124SN/A * Vector of per-thread instruction-based event queues. Used for 207124SN/A * scheduling events based on number of instructions committed by 208124SN/A * a particular thread. 209124SN/A */ 210503SN/A EventQueue **comInstEventQueue; 2112SN/A 212124SN/A /** 213124SN/A * Vector of per-thread load-based event queues. Used for 214124SN/A * scheduling events based on number of loads committed by 215124SN/A *a particular thread. 216124SN/A */ 217124SN/A EventQueue **comLoadEventQueue; 218124SN/A 2192SN/A System *system; 220921SN/A 2213661Srdreslin@umich.edu Tick phase; 2223661Srdreslin@umich.edu 2232378SN/A#if FULL_SYSTEM 224921SN/A /** 225921SN/A * Serialize this object to the given output stream. 226921SN/A * @param os The stream to serialize to. 227921SN/A */ 228921SN/A virtual void serialize(std::ostream &os); 229921SN/A 230921SN/A /** 231921SN/A * Reconstruct the state of this object from a checkpoint. 232921SN/A * @param cp The checkpoint use. 233921SN/A * @param section The section name of this object 234921SN/A */ 235921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 236921SN/A 2372SN/A#endif 2382SN/A 239124SN/A /** 240124SN/A * Return pointer to CPU's branch predictor (NULL if none). 241124SN/A * @return Branch predictor pointer. 242124SN/A */ 2432SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2442SN/A 245707SN/A virtual Counter totalInstructions() const { return 0; } 246707SN/A 2471191SN/A // Function tracing 2481191SN/A private: 2491191SN/A bool functionTracingEnabled; 2501191SN/A std::ostream *functionTraceStream; 2511191SN/A Addr currentFunctionStart; 2521191SN/A Addr currentFunctionEnd; 2531191SN/A Tick functionEntryTick; 2541191SN/A void enableFunctionTrace(); 2551191SN/A void traceFunctionsInternal(Addr pc); 2561191SN/A 2571191SN/A protected: 2581191SN/A void traceFunctions(Addr pc) 2591191SN/A { 2601191SN/A if (functionTracingEnabled) 2611191SN/A traceFunctionsInternal(pc); 2621191SN/A } 2631191SN/A 2642SN/A private: 2652SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2662SN/A 2672SN/A public: 2682SN/A static int numSimulatedCPUs() { return cpuList.size(); } 269707SN/A static Counter numSimulatedInstructions() 270707SN/A { 271707SN/A Counter total = 0; 272707SN/A 273707SN/A int size = cpuList.size(); 274707SN/A for (int i = 0; i < size; ++i) 275707SN/A total += cpuList[i]->totalInstructions(); 276707SN/A 277707SN/A return total; 278707SN/A } 279707SN/A 280707SN/A public: 281707SN/A // Number of CPU cycles simulated 282729SN/A Stats::Scalar<> numCycles; 2832SN/A}; 2842SN/A 2851717SN/A#endif // __CPU_BASE_HH__ 286