base.hh revision 5645
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 38707SN/A#include "base/statistics.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/eventq.hh" 414776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 422856Srdreslin@umich.edu#include "mem/mem_object.hh" 432SN/A 443520Sgblack@eecs.umich.edu#if FULL_SYSTEM 453520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 463520Sgblack@eecs.umich.edu#endif 473520Sgblack@eecs.umich.edu 485529Snate@binkert.orgclass BaseCPUParams; 492190SN/Aclass BranchPred; 502315SN/Aclass CheckerCPU; 512680Sktlim@umich.educlass ThreadContext; 522SN/Aclass System; 532856Srdreslin@umich.educlass Port; 542SN/A 554182Sgblack@eecs.umich.edunamespace TheISA 564182Sgblack@eecs.umich.edu{ 574182Sgblack@eecs.umich.edu class Predecoder; 584182Sgblack@eecs.umich.edu} 594182Sgblack@eecs.umich.edu 602356SN/Aclass CPUProgressEvent : public Event 612356SN/A{ 622356SN/A protected: 632356SN/A Tick interval; 642356SN/A Counter lastNumInst; 652356SN/A BaseCPU *cpu; 662356SN/A 672356SN/A public: 685606Snate@binkert.org CPUProgressEvent(BaseCPU *_cpu, Tick ival); 692356SN/A 702356SN/A void process(); 712356SN/A 725336Shines@cs.fsu.edu virtual const char *description() const; 732356SN/A}; 742356SN/A 752856Srdreslin@umich.educlass BaseCPU : public MemObject 762SN/A{ 771634SN/A protected: 781634SN/A // CPU's clock period in terms of the number of ticks of curTime. 791695SN/A Tick clock; 803814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 813814Ssaidi@eecs.umich.edu Tick instCnt; 821634SN/A 831634SN/A public: 842359SN/A// Tick currentTick; 851695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 865100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 871695SN/A inline Tick curCycle() const { return curTick / clock; } 885099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 893814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 903814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 911634SN/A 923495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 933495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 943495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 953495Sktlim@umich.edu */ 963495Sktlim@umich.edu Tick nextCycle(); 973495Sktlim@umich.edu 983495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 993495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 1003495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1013495Sktlim@umich.edu * current cycle. 1023495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1033495Sktlim@umich.edu */ 1043495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1053495Sktlim@umich.edu 1061858SN/A#if FULL_SYSTEM 1072SN/A protected: 1083520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1093520Sgblack@eecs.umich.edu// uint64_t intstatus; 1103520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1112SN/A 1122SN/A public: 1135645Sgblack@eecs.umich.edu TheISA::Interrupts * 1145645Sgblack@eecs.umich.edu getInterruptController() 1155645Sgblack@eecs.umich.edu { 1165645Sgblack@eecs.umich.edu return &interrupts; 1175645Sgblack@eecs.umich.edu } 1185645Sgblack@eecs.umich.edu 1192SN/A virtual void post_interrupt(int int_num, int index); 1202SN/A virtual void clear_interrupt(int int_num, int index); 1212SN/A virtual void clear_interrupts(); 1224103Ssaidi@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1232SN/A 1243521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1253521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1261917SN/A 1271917SN/A class ProfileEvent : public Event 1281917SN/A { 1291917SN/A private: 1301917SN/A BaseCPU *cpu; 1315536Srstrong@hp.com Tick interval; 1321917SN/A 1331917SN/A public: 1345536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 1351917SN/A void process(); 1361917SN/A }; 1371917SN/A ProfileEvent *profileEvent; 1382SN/A#endif 1392SN/A 1402SN/A protected: 1412680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1424182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1432SN/A 1444776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1454776Sgblack@eecs.umich.edu 1462SN/A public: 147393SN/A 1484776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1494776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1504776Sgblack@eecs.umich.edu 151393SN/A /// Notify the CPU that the indicated context is now active. The 152393SN/A /// delay parameter indicates the number of ticks to wait before 153393SN/A /// executing (typically 0 or 1). 154393SN/A virtual void activateContext(int thread_num, int delay) {} 155393SN/A 156393SN/A /// Notify the CPU that the indicated context is now suspended. 157393SN/A virtual void suspendContext(int thread_num) {} 158393SN/A 159393SN/A /// Notify the CPU that the indicated context is now deallocated. 160393SN/A virtual void deallocateContext(int thread_num) {} 161393SN/A 162393SN/A /// Notify the CPU that the indicated context is now halted. 163393SN/A virtual void haltContext(int thread_num) {} 1642SN/A 1654000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1664000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1674000Ssaidi@eecs.umich.edu 1684000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1694000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1704000Ssaidi@eecs.umich.edu 1712SN/A public: 1725529Snate@binkert.org typedef BaseCPUParams Params; 1735529Snate@binkert.org const Params *params() const 1745529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 1751400SN/A BaseCPU(Params *params); 1761191SN/A virtual ~BaseCPU(); 1772SN/A 1781129SN/A virtual void init(); 1791917SN/A virtual void startup(); 1802SN/A virtual void regStats(); 1812SN/A 1822103SN/A virtual void activateWhenReady(int tid) {}; 1832103SN/A 1842680Sktlim@umich.edu void registerThreadContexts(); 185180SN/A 1861492SN/A /// Prepare for another CPU to take over execution. When it is 1871492SN/A /// is ready (drained pipe) it signals the sampler. 1882798Sktlim@umich.edu virtual void switchOut(); 189180SN/A 190180SN/A /// Take over execution from the given CPU. Used for warm-up and 191180SN/A /// sampling. 1924192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 193180SN/A 194124SN/A /** 195124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 196124SN/A * This is a constant for the duration of the simulation. 197124SN/A */ 1982SN/A int number_of_threads; 1992SN/A 2005529Snate@binkert.org TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 2015529Snate@binkert.org 202124SN/A /** 203124SN/A * Vector of per-thread instruction-based event queues. Used for 204124SN/A * scheduling events based on number of instructions committed by 205124SN/A * a particular thread. 206124SN/A */ 207503SN/A EventQueue **comInstEventQueue; 2082SN/A 209124SN/A /** 210124SN/A * Vector of per-thread load-based event queues. Used for 211124SN/A * scheduling events based on number of loads committed by 212124SN/A *a particular thread. 213124SN/A */ 214124SN/A EventQueue **comLoadEventQueue; 215124SN/A 2162SN/A System *system; 217921SN/A 2183661Srdreslin@umich.edu Tick phase; 2193661Srdreslin@umich.edu 2202378SN/A#if FULL_SYSTEM 221921SN/A /** 222921SN/A * Serialize this object to the given output stream. 223921SN/A * @param os The stream to serialize to. 224921SN/A */ 225921SN/A virtual void serialize(std::ostream &os); 226921SN/A 227921SN/A /** 228921SN/A * Reconstruct the state of this object from a checkpoint. 229921SN/A * @param cp The checkpoint use. 230921SN/A * @param section The section name of this object 231921SN/A */ 232921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 233921SN/A 2342SN/A#endif 2352SN/A 236124SN/A /** 237124SN/A * Return pointer to CPU's branch predictor (NULL if none). 238124SN/A * @return Branch predictor pointer. 239124SN/A */ 2402SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2412SN/A 242707SN/A virtual Counter totalInstructions() const { return 0; } 243707SN/A 2441191SN/A // Function tracing 2451191SN/A private: 2461191SN/A bool functionTracingEnabled; 2471191SN/A std::ostream *functionTraceStream; 2481191SN/A Addr currentFunctionStart; 2491191SN/A Addr currentFunctionEnd; 2501191SN/A Tick functionEntryTick; 2511191SN/A void enableFunctionTrace(); 2521191SN/A void traceFunctionsInternal(Addr pc); 2531191SN/A 2541191SN/A protected: 2551191SN/A void traceFunctions(Addr pc) 2561191SN/A { 2571191SN/A if (functionTracingEnabled) 2581191SN/A traceFunctionsInternal(pc); 2591191SN/A } 2601191SN/A 2612SN/A private: 2622SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2632SN/A 2642SN/A public: 2652SN/A static int numSimulatedCPUs() { return cpuList.size(); } 266707SN/A static Counter numSimulatedInstructions() 267707SN/A { 268707SN/A Counter total = 0; 269707SN/A 270707SN/A int size = cpuList.size(); 271707SN/A for (int i = 0; i < size; ++i) 272707SN/A total += cpuList[i]->totalInstructions(); 273707SN/A 274707SN/A return total; 275707SN/A } 276707SN/A 277707SN/A public: 278707SN/A // Number of CPU cycles simulated 279729SN/A Stats::Scalar<> numCycles; 2802SN/A}; 2812SN/A 2821717SN/A#endif // __CPU_BASE_HH__ 283