base.hh revision 5338
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 38707SN/A#include "base/statistics.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/eventq.hh" 414776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 422856Srdreslin@umich.edu#include "mem/mem_object.hh" 432SN/A 443520Sgblack@eecs.umich.edu#if FULL_SYSTEM 453520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 463520Sgblack@eecs.umich.edu#endif 473520Sgblack@eecs.umich.edu 482190SN/Aclass BranchPred; 492315SN/Aclass CheckerCPU; 502680Sktlim@umich.educlass ThreadContext; 512SN/Aclass System; 522856Srdreslin@umich.educlass Port; 532SN/A 544182Sgblack@eecs.umich.edunamespace TheISA 554182Sgblack@eecs.umich.edu{ 564182Sgblack@eecs.umich.edu class Predecoder; 574182Sgblack@eecs.umich.edu} 584182Sgblack@eecs.umich.edu 592356SN/Aclass CPUProgressEvent : public Event 602356SN/A{ 612356SN/A protected: 622356SN/A Tick interval; 632356SN/A Counter lastNumInst; 642356SN/A BaseCPU *cpu; 652356SN/A 662356SN/A public: 673126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 682356SN/A 692356SN/A void process(); 702356SN/A 715336Shines@cs.fsu.edu virtual const char *description() const; 722356SN/A}; 732356SN/A 742856Srdreslin@umich.educlass BaseCPU : public MemObject 752SN/A{ 761634SN/A protected: 771634SN/A // CPU's clock period in terms of the number of ticks of curTime. 781695SN/A Tick clock; 793814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 803814Ssaidi@eecs.umich.edu Tick instCnt; 811634SN/A 821634SN/A public: 832359SN/A// Tick currentTick; 841695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 855100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 861695SN/A inline Tick curCycle() const { return curTick / clock; } 875099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 883814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 893814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 901634SN/A 913495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 923495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 933495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 943495Sktlim@umich.edu */ 953495Sktlim@umich.edu Tick nextCycle(); 963495Sktlim@umich.edu 973495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 983495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 993495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1003495Sktlim@umich.edu * current cycle. 1013495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1023495Sktlim@umich.edu */ 1033495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1043495Sktlim@umich.edu 1051858SN/A#if FULL_SYSTEM 1062SN/A protected: 1073520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1083520Sgblack@eecs.umich.edu// uint64_t intstatus; 1093520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1102SN/A 1112SN/A public: 1122SN/A virtual void post_interrupt(int int_num, int index); 1132SN/A virtual void clear_interrupt(int int_num, int index); 1142SN/A virtual void clear_interrupts(); 1154103Ssaidi@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1162SN/A 1173521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1183521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1191917SN/A 1201917SN/A class ProfileEvent : public Event 1211917SN/A { 1221917SN/A private: 1231917SN/A BaseCPU *cpu; 1241917SN/A int interval; 1251917SN/A 1261917SN/A public: 1271917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1281917SN/A void process(); 1291917SN/A }; 1301917SN/A ProfileEvent *profileEvent; 1312SN/A#endif 1322SN/A 1332SN/A protected: 1342680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1354182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1362SN/A 1374776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1384776Sgblack@eecs.umich.edu 1392SN/A public: 140393SN/A 1414776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1424776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1434776Sgblack@eecs.umich.edu 144393SN/A /// Notify the CPU that the indicated context is now active. The 145393SN/A /// delay parameter indicates the number of ticks to wait before 146393SN/A /// executing (typically 0 or 1). 147393SN/A virtual void activateContext(int thread_num, int delay) {} 148393SN/A 149393SN/A /// Notify the CPU that the indicated context is now suspended. 150393SN/A virtual void suspendContext(int thread_num) {} 151393SN/A 152393SN/A /// Notify the CPU that the indicated context is now deallocated. 153393SN/A virtual void deallocateContext(int thread_num) {} 154393SN/A 155393SN/A /// Notify the CPU that the indicated context is now halted. 156393SN/A virtual void haltContext(int thread_num) {} 1572SN/A 1584000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1594000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1604000Ssaidi@eecs.umich.edu 1614000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1624000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1634000Ssaidi@eecs.umich.edu 1642SN/A public: 1651400SN/A struct Params 1661400SN/A { 1671400SN/A std::string name; 1681400SN/A int numberOfThreads; 1691400SN/A bool deferRegistration; 1701400SN/A Counter max_insts_any_thread; 1711400SN/A Counter max_insts_all_threads; 1721400SN/A Counter max_loads_any_thread; 1731400SN/A Counter max_loads_all_threads; 1741695SN/A Tick clock; 1751400SN/A bool functionTrace; 1761400SN/A Tick functionTraceStart; 1772378SN/A System *system; 1783170Sstever@eecs.umich.edu int cpu_id; 1794776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1804776Sgblack@eecs.umich.edu 1813661Srdreslin@umich.edu Tick phase; 1821858SN/A#if FULL_SYSTEM 1831917SN/A Tick profile; 1843617Sbinkertn@umich.edu 1853617Sbinkertn@umich.edu bool do_statistics_insts; 1863617Sbinkertn@umich.edu bool do_checkpoint_insts; 1873617Sbinkertn@umich.edu bool do_quiesce; 1881400SN/A#endif 1892356SN/A Tick progress_interval; 1902315SN/A BaseCPU *checker; 1911917SN/A 1925252Sksewell@umich.edu TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 1935222Sksewell@umich.edu 1941917SN/A Params(); 1951400SN/A }; 1962SN/A 1971400SN/A const Params *params; 1982SN/A 1991400SN/A BaseCPU(Params *params); 2001191SN/A virtual ~BaseCPU(); 2012SN/A 2021129SN/A virtual void init(); 2031917SN/A virtual void startup(); 2042SN/A virtual void regStats(); 2052SN/A 2062103SN/A virtual void activateWhenReady(int tid) {}; 2072103SN/A 2082680Sktlim@umich.edu void registerThreadContexts(); 209180SN/A 2101492SN/A /// Prepare for another CPU to take over execution. When it is 2111492SN/A /// is ready (drained pipe) it signals the sampler. 2122798Sktlim@umich.edu virtual void switchOut(); 213180SN/A 214180SN/A /// Take over execution from the given CPU. Used for warm-up and 215180SN/A /// sampling. 2164192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 217180SN/A 218124SN/A /** 219124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 220124SN/A * This is a constant for the duration of the simulation. 221124SN/A */ 2222SN/A int number_of_threads; 2232SN/A 224124SN/A /** 225124SN/A * Vector of per-thread instruction-based event queues. Used for 226124SN/A * scheduling events based on number of instructions committed by 227124SN/A * a particular thread. 228124SN/A */ 229503SN/A EventQueue **comInstEventQueue; 2302SN/A 231124SN/A /** 232124SN/A * Vector of per-thread load-based event queues. Used for 233124SN/A * scheduling events based on number of loads committed by 234124SN/A *a particular thread. 235124SN/A */ 236124SN/A EventQueue **comLoadEventQueue; 237124SN/A 2382SN/A System *system; 239921SN/A 2403661Srdreslin@umich.edu Tick phase; 2413661Srdreslin@umich.edu 2422378SN/A#if FULL_SYSTEM 243921SN/A /** 244921SN/A * Serialize this object to the given output stream. 245921SN/A * @param os The stream to serialize to. 246921SN/A */ 247921SN/A virtual void serialize(std::ostream &os); 248921SN/A 249921SN/A /** 250921SN/A * Reconstruct the state of this object from a checkpoint. 251921SN/A * @param cp The checkpoint use. 252921SN/A * @param section The section name of this object 253921SN/A */ 254921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 255921SN/A 2562SN/A#endif 2572SN/A 258124SN/A /** 259124SN/A * Return pointer to CPU's branch predictor (NULL if none). 260124SN/A * @return Branch predictor pointer. 261124SN/A */ 2622SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2632SN/A 264707SN/A virtual Counter totalInstructions() const { return 0; } 265707SN/A 2661191SN/A // Function tracing 2671191SN/A private: 2681191SN/A bool functionTracingEnabled; 2691191SN/A std::ostream *functionTraceStream; 2701191SN/A Addr currentFunctionStart; 2711191SN/A Addr currentFunctionEnd; 2721191SN/A Tick functionEntryTick; 2731191SN/A void enableFunctionTrace(); 2741191SN/A void traceFunctionsInternal(Addr pc); 2751191SN/A 2761191SN/A protected: 2771191SN/A void traceFunctions(Addr pc) 2781191SN/A { 2791191SN/A if (functionTracingEnabled) 2801191SN/A traceFunctionsInternal(pc); 2811191SN/A } 2821191SN/A 2832SN/A private: 2842SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2852SN/A 2862SN/A public: 2872SN/A static int numSimulatedCPUs() { return cpuList.size(); } 288707SN/A static Counter numSimulatedInstructions() 289707SN/A { 290707SN/A Counter total = 0; 291707SN/A 292707SN/A int size = cpuList.size(); 293707SN/A for (int i = 0; i < size; ++i) 294707SN/A total += cpuList[i]->totalInstructions(); 295707SN/A 296707SN/A return total; 297707SN/A } 298707SN/A 299707SN/A public: 300707SN/A // Number of CPU cycles simulated 301729SN/A Stats::Scalar<> numCycles; 3022SN/A}; 3032SN/A 3041717SN/A#endif // __CPU_BASE_HH__ 305