base.hh revision 5336
19020Sgblack@eecs.umich.edu/* 29020Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 39020Sgblack@eecs.umich.edu * All rights reserved. 49020Sgblack@eecs.umich.edu * 59020Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 69020Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 79020Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 89020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 99020Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 109020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 119020Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 129020Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 139020Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 149020Sgblack@eecs.umich.edu * this software without specific prior written permission. 159020Sgblack@eecs.umich.edu * 169020Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179020Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189020Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199020Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209020Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219020Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229020Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239020Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249020Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259020Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269020Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279020Sgblack@eecs.umich.edu * 289020Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 299020Sgblack@eecs.umich.edu * Nathan Binkert 309020Sgblack@eecs.umich.edu */ 319020Sgblack@eecs.umich.edu 329020Sgblack@eecs.umich.edu#ifndef __CPU_BASE_HH__ 339020Sgblack@eecs.umich.edu#define __CPU_BASE_HH__ 349024Sgblack@eecs.umich.edu 359023Sgblack@eecs.umich.edu#include <vector> 369023Sgblack@eecs.umich.edu 379023Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 389024Sgblack@eecs.umich.edu#include "base/statistics.hh" 399020Sgblack@eecs.umich.edu#include "config/full_system.hh" 409023Sgblack@eecs.umich.edu#include "sim/eventq.hh" 419023Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 429020Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 439020Sgblack@eecs.umich.edu 449020Sgblack@eecs.umich.edu#if FULL_SYSTEM 459022Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 469022Sgblack@eecs.umich.edu#endif 479022Sgblack@eecs.umich.edu 489023Sgblack@eecs.umich.educlass BranchPred; 499023Sgblack@eecs.umich.educlass CheckerCPU; 509023Sgblack@eecs.umich.educlass ThreadContext; 519023Sgblack@eecs.umich.educlass System; 529023Sgblack@eecs.umich.educlass Port; 539023Sgblack@eecs.umich.edu 549023Sgblack@eecs.umich.edunamespace TheISA 559023Sgblack@eecs.umich.edu{ 569023Sgblack@eecs.umich.edu class Predecoder; 579023Sgblack@eecs.umich.edu} 589023Sgblack@eecs.umich.edu 599023Sgblack@eecs.umich.educlass CPUProgressEvent : public Event 609023Sgblack@eecs.umich.edu{ 619023Sgblack@eecs.umich.edu protected: 629023Sgblack@eecs.umich.edu Tick interval; 639023Sgblack@eecs.umich.edu Counter lastNumInst; 649023Sgblack@eecs.umich.edu BaseCPU *cpu; 659023Sgblack@eecs.umich.edu 669023Sgblack@eecs.umich.edu public: 679023Sgblack@eecs.umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 689023Sgblack@eecs.umich.edu 699023Sgblack@eecs.umich.edu void process(); 709023Sgblack@eecs.umich.edu 719023Sgblack@eecs.umich.edu virtual const char *description() const; 729023Sgblack@eecs.umich.edu}; 739023Sgblack@eecs.umich.edu 749023Sgblack@eecs.umich.educlass BaseCPU : public MemObject 759023Sgblack@eecs.umich.edu{ 769023Sgblack@eecs.umich.edu protected: 779023Sgblack@eecs.umich.edu // CPU's clock period in terms of the number of ticks of curTime. 789023Sgblack@eecs.umich.edu Tick clock; 799023Sgblack@eecs.umich.edu // @todo remove me after debugging with legion done 809023Sgblack@eecs.umich.edu Tick instCnt; 819023Sgblack@eecs.umich.edu 829023Sgblack@eecs.umich.edu public: 839023Sgblack@eecs.umich.edu// Tick currentTick; 849023Sgblack@eecs.umich.edu inline Tick frequency() const { return Clock::Frequency / clock; } 859023Sgblack@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 869023Sgblack@eecs.umich.edu inline Tick curCycle() const { return curTick / clock; } 879023Sgblack@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 889023Sgblack@eecs.umich.edu // @todo remove me after debugging with legion done 899023Sgblack@eecs.umich.edu Tick instCount() { return instCnt; } 909023Sgblack@eecs.umich.edu 919023Sgblack@eecs.umich.edu /** The next cycle the CPU should be scheduled, given a cache 929023Sgblack@eecs.umich.edu * access or quiesce event returning on this cycle. This function 939023Sgblack@eecs.umich.edu * may return curTick if the CPU should run on the current cycle. 949023Sgblack@eecs.umich.edu */ 959023Sgblack@eecs.umich.edu Tick nextCycle(); 969023Sgblack@eecs.umich.edu 979023Sgblack@eecs.umich.edu /** The next cycle the CPU should be scheduled, given a cache 989023Sgblack@eecs.umich.edu * access or quiesce event returning on the given Tick. This 999023Sgblack@eecs.umich.edu * function may return curTick if the CPU should run on the 1009023Sgblack@eecs.umich.edu * current cycle. 1019022Sgblack@eecs.umich.edu * @param begin_tick The tick that the event is completing on. 1029024Sgblack@eecs.umich.edu */ 1039022Sgblack@eecs.umich.edu Tick nextCycle(Tick begin_tick); 1049022Sgblack@eecs.umich.edu 1059022Sgblack@eecs.umich.edu#if FULL_SYSTEM 1069022Sgblack@eecs.umich.edu protected: 1079022Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1089022Sgblack@eecs.umich.edu// uint64_t intstatus; 1099022Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1109022Sgblack@eecs.umich.edu 1119022Sgblack@eecs.umich.edu public: 1129022Sgblack@eecs.umich.edu virtual void post_interrupt(int int_num, int index); 1139022Sgblack@eecs.umich.edu virtual void clear_interrupt(int int_num, int index); 1149022Sgblack@eecs.umich.edu virtual void clear_interrupts(); 1159023Sgblack@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1169023Sgblack@eecs.umich.edu 1179023Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1189023Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1199023Sgblack@eecs.umich.edu 1209023Sgblack@eecs.umich.edu class ProfileEvent : public Event 1219023Sgblack@eecs.umich.edu { 1229023Sgblack@eecs.umich.edu private: 1239023Sgblack@eecs.umich.edu BaseCPU *cpu; 1249022Sgblack@eecs.umich.edu int interval; 1259020Sgblack@eecs.umich.edu 1269020Sgblack@eecs.umich.edu public: 1279020Sgblack@eecs.umich.edu ProfileEvent(BaseCPU *cpu, int interval); 1289020Sgblack@eecs.umich.edu void process(); 129 }; 130 ProfileEvent *profileEvent; 131#endif 132 133 protected: 134 std::vector<ThreadContext *> threadContexts; 135 std::vector<TheISA::Predecoder *> predecoders; 136 137 Trace::InstTracer * tracer; 138 139 public: 140 141 /// Provide access to the tracer pointer 142 Trace::InstTracer * getTracer() { return tracer; } 143 144 /// Notify the CPU that the indicated context is now active. The 145 /// delay parameter indicates the number of ticks to wait before 146 /// executing (typically 0 or 1). 147 virtual void activateContext(int thread_num, int delay) {} 148 149 /// Notify the CPU that the indicated context is now suspended. 150 virtual void suspendContext(int thread_num) {} 151 152 /// Notify the CPU that the indicated context is now deallocated. 153 virtual void deallocateContext(int thread_num) {} 154 155 /// Notify the CPU that the indicated context is now halted. 156 virtual void haltContext(int thread_num) {} 157 158 /// Given a Thread Context pointer return the thread num 159 int findContext(ThreadContext *tc); 160 161 /// Given a thread num get tho thread context for it 162 ThreadContext *getContext(int tn) { return threadContexts[tn]; } 163 164 public: 165 struct Params 166 { 167 std::string name; 168 int numberOfThreads; 169 bool deferRegistration; 170 Counter max_insts_any_thread; 171 Counter max_insts_all_threads; 172 Counter max_loads_any_thread; 173 Counter max_loads_all_threads; 174 Tick clock; 175 bool functionTrace; 176 Tick functionTraceStart; 177 System *system; 178 int cpu_id; 179 Trace::InstTracer * tracer; 180 181 Tick phase; 182#if FULL_SYSTEM 183 Tick profile; 184 185 bool do_statistics_insts; 186 bool do_checkpoint_insts; 187 bool do_quiesce; 188#endif 189 Tick progress_interval; 190 BaseCPU *checker; 191 192 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core 193 194 Params(); 195 }; 196 197 const Params *params; 198 199 BaseCPU(Params *params); 200 virtual ~BaseCPU(); 201 202 virtual void init(); 203 virtual void startup(); 204 virtual void regStats(); 205 206 virtual void activateWhenReady(int tid) {}; 207 208 void registerThreadContexts(); 209 210 /// Prepare for another CPU to take over execution. When it is 211 /// is ready (drained pipe) it signals the sampler. 212 virtual void switchOut(); 213 214 /// Take over execution from the given CPU. Used for warm-up and 215 /// sampling. 216 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 217 218 /** 219 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 220 * This is a constant for the duration of the simulation. 221 */ 222 int number_of_threads; 223 224 /** 225 * Vector of per-thread instruction-based event queues. Used for 226 * scheduling events based on number of instructions committed by 227 * a particular thread. 228 */ 229 EventQueue **comInstEventQueue; 230 231 /** 232 * Vector of per-thread load-based event queues. Used for 233 * scheduling events based on number of loads committed by 234 *a particular thread. 235 */ 236 EventQueue **comLoadEventQueue; 237 238 System *system; 239 240 Tick phase; 241 242#if FULL_SYSTEM 243 /** 244 * Serialize this object to the given output stream. 245 * @param os The stream to serialize to. 246 */ 247 virtual void serialize(std::ostream &os); 248 249 /** 250 * Reconstruct the state of this object from a checkpoint. 251 * @param cp The checkpoint use. 252 * @param section The section name of this object 253 */ 254 virtual void unserialize(Checkpoint *cp, const std::string §ion); 255 256#endif 257 258 /** 259 * Return pointer to CPU's branch predictor (NULL if none). 260 * @return Branch predictor pointer. 261 */ 262 virtual BranchPred *getBranchPred() { return NULL; }; 263 264 virtual Counter totalInstructions() const { return 0; } 265 266 // Function tracing 267 private: 268 bool functionTracingEnabled; 269 std::ostream *functionTraceStream; 270 Addr currentFunctionStart; 271 Addr currentFunctionEnd; 272 Tick functionEntryTick; 273 void enableFunctionTrace(); 274 void traceFunctionsInternal(Addr pc); 275 276 protected: 277 void traceFunctions(Addr pc) 278 { 279 if (functionTracingEnabled) 280 traceFunctionsInternal(pc); 281 } 282 283 private: 284 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 285 286 public: 287 static int numSimulatedCPUs() { return cpuList.size(); } 288 static Counter numSimulatedInstructions() 289 { 290 Counter total = 0; 291 292 int size = cpuList.size(); 293 for (int i = 0; i < size; ++i) 294 total += cpuList[i]->totalInstructions(); 295 296 return total; 297 } 298 299 public: 300 // Number of CPU cycles simulated 301 Stats::Scalar<> numCycles; 302}; 303 304#endif // __CPU_BASE_HH__ 305