base.hh revision 5222
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 38707SN/A#include "base/statistics.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/eventq.hh" 414776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 422856Srdreslin@umich.edu#include "mem/mem_object.hh" 432SN/A 443520Sgblack@eecs.umich.edu#if FULL_SYSTEM 453520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 463520Sgblack@eecs.umich.edu#endif 473520Sgblack@eecs.umich.edu 482190SN/Aclass BranchPred; 492315SN/Aclass CheckerCPU; 502680Sktlim@umich.educlass ThreadContext; 512SN/Aclass System; 522856Srdreslin@umich.educlass Port; 532SN/A 544182Sgblack@eecs.umich.edunamespace TheISA 554182Sgblack@eecs.umich.edu{ 564182Sgblack@eecs.umich.edu class Predecoder; 574182Sgblack@eecs.umich.edu} 584182Sgblack@eecs.umich.edu 592356SN/Aclass CPUProgressEvent : public Event 602356SN/A{ 612356SN/A protected: 622356SN/A Tick interval; 632356SN/A Counter lastNumInst; 642356SN/A BaseCPU *cpu; 652356SN/A 662356SN/A public: 673126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 682356SN/A 692356SN/A void process(); 702356SN/A 712356SN/A virtual const char *description(); 722356SN/A}; 732356SN/A 742856Srdreslin@umich.educlass BaseCPU : public MemObject 752SN/A{ 761634SN/A protected: 771634SN/A // CPU's clock period in terms of the number of ticks of curTime. 781695SN/A Tick clock; 793814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 803814Ssaidi@eecs.umich.edu Tick instCnt; 811634SN/A 821634SN/A public: 832359SN/A// Tick currentTick; 841695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 855100Ssaidi@eecs.umich.edu inline Tick ticks(int numCycles) const { return clock * numCycles; } 861695SN/A inline Tick curCycle() const { return curTick / clock; } 875099Ssaidi@eecs.umich.edu inline Tick tickToCycles(Tick val) const { return val / clock; } 883814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 893814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 901634SN/A 913495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 923495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 933495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 943495Sktlim@umich.edu */ 953495Sktlim@umich.edu Tick nextCycle(); 963495Sktlim@umich.edu 973495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 983495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 993495Sktlim@umich.edu * function may return curTick if the CPU should run on the 1003495Sktlim@umich.edu * current cycle. 1013495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1023495Sktlim@umich.edu */ 1033495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1043495Sktlim@umich.edu 1051858SN/A#if FULL_SYSTEM 1062SN/A protected: 1073520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1083520Sgblack@eecs.umich.edu// uint64_t intstatus; 1093520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1102SN/A 1112SN/A public: 1122SN/A virtual void post_interrupt(int int_num, int index); 1132SN/A virtual void clear_interrupt(int int_num, int index); 1142SN/A virtual void clear_interrupts(); 1154103Ssaidi@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1162SN/A 1173521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1183521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1191917SN/A 1201917SN/A class ProfileEvent : public Event 1211917SN/A { 1221917SN/A private: 1231917SN/A BaseCPU *cpu; 1241917SN/A int interval; 1251917SN/A 1261917SN/A public: 1271917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1281917SN/A void process(); 1291917SN/A }; 1301917SN/A ProfileEvent *profileEvent; 1312SN/A#endif 1322SN/A 1332SN/A protected: 1342680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1354182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1362SN/A 1374776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1384776Sgblack@eecs.umich.edu 1392SN/A public: 140393SN/A 1414776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1424776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1434776Sgblack@eecs.umich.edu 144393SN/A /// Notify the CPU that the indicated context is now active. The 145393SN/A /// delay parameter indicates the number of ticks to wait before 146393SN/A /// executing (typically 0 or 1). 147393SN/A virtual void activateContext(int thread_num, int delay) {} 148393SN/A 149393SN/A /// Notify the CPU that the indicated context is now suspended. 150393SN/A virtual void suspendContext(int thread_num) {} 151393SN/A 152393SN/A /// Notify the CPU that the indicated context is now deallocated. 153393SN/A virtual void deallocateContext(int thread_num) {} 154393SN/A 155393SN/A /// Notify the CPU that the indicated context is now halted. 156393SN/A virtual void haltContext(int thread_num) {} 1572SN/A 1584000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1594000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1604000Ssaidi@eecs.umich.edu 1614000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1624000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1634000Ssaidi@eecs.umich.edu 1642SN/A public: 1651400SN/A struct Params 1661400SN/A { 1671400SN/A std::string name; 1681400SN/A int numberOfThreads; 1691400SN/A bool deferRegistration; 1701400SN/A Counter max_insts_any_thread; 1711400SN/A Counter max_insts_all_threads; 1721400SN/A Counter max_loads_any_thread; 1731400SN/A Counter max_loads_all_threads; 1741695SN/A Tick clock; 1751400SN/A bool functionTrace; 1761400SN/A Tick functionTraceStart; 1772378SN/A System *system; 1783170Sstever@eecs.umich.edu int cpu_id; 1794776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1804776Sgblack@eecs.umich.edu 1813661Srdreslin@umich.edu Tick phase; 1821858SN/A#if FULL_SYSTEM 1831917SN/A Tick profile; 1843617Sbinkertn@umich.edu 1853617Sbinkertn@umich.edu bool do_statistics_insts; 1863617Sbinkertn@umich.edu bool do_checkpoint_insts; 1873617Sbinkertn@umich.edu bool do_quiesce; 1881400SN/A#endif 1892356SN/A Tick progress_interval; 1902315SN/A BaseCPU *checker; 1911917SN/A 1925222Sksewell@umich.edu#if THE_ISA == MIPS_ISA 1935222Sksewell@umich.edu /* Note: It looks like it will be better to allow simulator users 1945222Sksewell@umich.edu to specify the values of individual variables instead of requiring 1955222Sksewell@umich.edu users to define the values of entire registers 1965222Sksewell@umich.edu Especially since a lot of these variables can be created from other 1975222Sksewell@umich.edu user parameters (cache descriptions) 1985222Sksewell@umich.edu -jpp 1995222Sksewell@umich.edu */ 2005222Sksewell@umich.edu // MIPS CP0 State - First individual variables 2015222Sksewell@umich.edu // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA) 2025222Sksewell@umich.edu unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt 2035222Sksewell@umich.edu unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt 2045222Sksewell@umich.edu unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set 2055222Sksewell@umich.edu unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options 2065222Sksewell@umich.edu unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS) 2075222Sksewell@umich.edu unsigned CP0_PRId_ProcessorID; // Page 105 2085222Sksewell@umich.edu unsigned CP0_PRId_Revision; // Page 105 2095222Sksewell@umich.edu unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system 2105222Sksewell@umich.edu unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode 2115222Sksewell@umich.edu unsigned CP0_Config_AT; //Page 109 2125222Sksewell@umich.edu unsigned CP0_Config_AR; //Page 109 2135222Sksewell@umich.edu unsigned CP0_Config_MT; //Page 109 2145222Sksewell@umich.edu unsigned CP0_Config_VI; //Page 109 2155222Sksewell@umich.edu unsigned CP0_Config1_M; // Page 110 2165222Sksewell@umich.edu unsigned CP0_Config1_MMU; // Page 110 2175222Sksewell@umich.edu unsigned CP0_Config1_IS; // Page 110 2185222Sksewell@umich.edu unsigned CP0_Config1_IL; // Page 111 2195222Sksewell@umich.edu unsigned CP0_Config1_IA; // Page 111 2205222Sksewell@umich.edu unsigned CP0_Config1_DS; // Page 111 2215222Sksewell@umich.edu unsigned CP0_Config1_DL; // Page 112 2225222Sksewell@umich.edu unsigned CP0_Config1_DA; // Page 112 2235222Sksewell@umich.edu bool CP0_Config1_C2; // Page 112 2245222Sksewell@umich.edu bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32 2255222Sksewell@umich.edu bool CP0_Config1_PC;// Page 112 2265222Sksewell@umich.edu bool CP0_Config1_WR;// Page 113 2275222Sksewell@umich.edu bool CP0_Config1_CA;// Page 113 2285222Sksewell@umich.edu bool CP0_Config1_EP;// Page 113 2295222Sksewell@umich.edu bool CP0_Config1_FP;// Page 113 2305222Sksewell@umich.edu bool CP0_Config2_M; // Page 114 2315222Sksewell@umich.edu unsigned CP0_Config2_TU;// Page 114 2325222Sksewell@umich.edu unsigned CP0_Config2_TS;// Page 114 2335222Sksewell@umich.edu unsigned CP0_Config2_TL;// Page 115 2345222Sksewell@umich.edu unsigned CP0_Config2_TA;// Page 115 2355222Sksewell@umich.edu unsigned CP0_Config2_SU;// Page 115 2365222Sksewell@umich.edu unsigned CP0_Config2_SS;// Page 115 2375222Sksewell@umich.edu unsigned CP0_Config2_SL;// Page 116 2385222Sksewell@umich.edu unsigned CP0_Config2_SA;// Page 116 2395222Sksewell@umich.edu bool CP0_Config3_M; //// Page 117 2405222Sksewell@umich.edu bool CP0_Config3_DSPP;// Page 117 2415222Sksewell@umich.edu bool CP0_Config3_LPA;// Page 117 2425222Sksewell@umich.edu bool CP0_Config3_VEIC;// Page 118 2435222Sksewell@umich.edu bool CP0_Config3_VInt; // Page 118 2445222Sksewell@umich.edu bool CP0_Config3_SP;// Page 118 2455222Sksewell@umich.edu bool CP0_Config3_MT;// Page 119 2465222Sksewell@umich.edu bool CP0_Config3_SM;// Page 119 2475222Sksewell@umich.edu bool CP0_Config3_TL;// Page 119 2485222Sksewell@umich.edu 2495222Sksewell@umich.edu bool CP0_WatchHi_M; // Page 124 2505222Sksewell@umich.edu bool CP0_PerfCtr_M; // Page 130 2515222Sksewell@umich.edu bool CP0_PerfCtr_W; // Page 130 2525222Sksewell@umich.edu 2535222Sksewell@umich.edu 2545222Sksewell@umich.edu // Then, whole registers 2555222Sksewell@umich.edu unsigned CP0_PRId; 2565222Sksewell@umich.edu unsigned CP0_Config; 2575222Sksewell@umich.edu unsigned CP0_Config1; 2585222Sksewell@umich.edu unsigned CP0_Config2; 2595222Sksewell@umich.edu unsigned CP0_Config3; 2605222Sksewell@umich.edu 2615222Sksewell@umich.edu#endif 2625222Sksewell@umich.edu 2631917SN/A Params(); 2641400SN/A }; 2652SN/A 2661400SN/A const Params *params; 2672SN/A 2681400SN/A BaseCPU(Params *params); 2691191SN/A virtual ~BaseCPU(); 2702SN/A 2711129SN/A virtual void init(); 2721917SN/A virtual void startup(); 2732SN/A virtual void regStats(); 2742SN/A 2752103SN/A virtual void activateWhenReady(int tid) {}; 2762103SN/A 2772680Sktlim@umich.edu void registerThreadContexts(); 278180SN/A 2791492SN/A /// Prepare for another CPU to take over execution. When it is 2801492SN/A /// is ready (drained pipe) it signals the sampler. 2812798Sktlim@umich.edu virtual void switchOut(); 282180SN/A 283180SN/A /// Take over execution from the given CPU. Used for warm-up and 284180SN/A /// sampling. 2854192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 286180SN/A 287124SN/A /** 288124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 289124SN/A * This is a constant for the duration of the simulation. 290124SN/A */ 2912SN/A int number_of_threads; 2922SN/A 293124SN/A /** 294124SN/A * Vector of per-thread instruction-based event queues. Used for 295124SN/A * scheduling events based on number of instructions committed by 296124SN/A * a particular thread. 297124SN/A */ 298503SN/A EventQueue **comInstEventQueue; 2992SN/A 300124SN/A /** 301124SN/A * Vector of per-thread load-based event queues. Used for 302124SN/A * scheduling events based on number of loads committed by 303124SN/A *a particular thread. 304124SN/A */ 305124SN/A EventQueue **comLoadEventQueue; 306124SN/A 3072SN/A System *system; 308921SN/A 3093661Srdreslin@umich.edu Tick phase; 3103661Srdreslin@umich.edu 3112378SN/A#if FULL_SYSTEM 312921SN/A /** 313921SN/A * Serialize this object to the given output stream. 314921SN/A * @param os The stream to serialize to. 315921SN/A */ 316921SN/A virtual void serialize(std::ostream &os); 317921SN/A 318921SN/A /** 319921SN/A * Reconstruct the state of this object from a checkpoint. 320921SN/A * @param cp The checkpoint use. 321921SN/A * @param section The section name of this object 322921SN/A */ 323921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 324921SN/A 3252SN/A#endif 3262SN/A 327124SN/A /** 328124SN/A * Return pointer to CPU's branch predictor (NULL if none). 329124SN/A * @return Branch predictor pointer. 330124SN/A */ 3312SN/A virtual BranchPred *getBranchPred() { return NULL; }; 3322SN/A 333707SN/A virtual Counter totalInstructions() const { return 0; } 334707SN/A 3351191SN/A // Function tracing 3361191SN/A private: 3371191SN/A bool functionTracingEnabled; 3381191SN/A std::ostream *functionTraceStream; 3391191SN/A Addr currentFunctionStart; 3401191SN/A Addr currentFunctionEnd; 3411191SN/A Tick functionEntryTick; 3421191SN/A void enableFunctionTrace(); 3431191SN/A void traceFunctionsInternal(Addr pc); 3441191SN/A 3451191SN/A protected: 3461191SN/A void traceFunctions(Addr pc) 3471191SN/A { 3481191SN/A if (functionTracingEnabled) 3491191SN/A traceFunctionsInternal(pc); 3501191SN/A } 3511191SN/A 3522SN/A private: 3532SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 3542SN/A 3552SN/A public: 3562SN/A static int numSimulatedCPUs() { return cpuList.size(); } 357707SN/A static Counter numSimulatedInstructions() 358707SN/A { 359707SN/A Counter total = 0; 360707SN/A 361707SN/A int size = cpuList.size(); 362707SN/A for (int i = 0; i < size; ++i) 363707SN/A total += cpuList[i]->totalInstructions(); 364707SN/A 365707SN/A return total; 366707SN/A } 367707SN/A 368707SN/A public: 369707SN/A // Number of CPU cycles simulated 370729SN/A Stats::Scalar<> numCycles; 3712SN/A}; 3722SN/A 3731717SN/A#endif // __CPU_BASE_HH__ 374