base.hh revision 4888
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 38707SN/A#include "base/statistics.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/eventq.hh" 412856Srdreslin@umich.edu#include "mem/mem_object.hh" 422SN/A 433520Sgblack@eecs.umich.edu#if FULL_SYSTEM 443520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 453520Sgblack@eecs.umich.edu#endif 463520Sgblack@eecs.umich.edu 472190SN/Aclass BranchPred; 482315SN/Aclass CheckerCPU; 492680Sktlim@umich.educlass ThreadContext; 502SN/Aclass System; 512856Srdreslin@umich.educlass Port; 522SN/A 534182Sgblack@eecs.umich.edunamespace TheISA 544182Sgblack@eecs.umich.edu{ 554182Sgblack@eecs.umich.edu class Predecoder; 564182Sgblack@eecs.umich.edu} 574182Sgblack@eecs.umich.edu 582356SN/Aclass CPUProgressEvent : public Event 592356SN/A{ 602356SN/A protected: 612356SN/A Tick interval; 622356SN/A Counter lastNumInst; 632356SN/A BaseCPU *cpu; 642356SN/A 652356SN/A public: 663126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 672356SN/A 682356SN/A void process(); 692356SN/A 702356SN/A virtual const char *description(); 712356SN/A}; 722356SN/A 732856Srdreslin@umich.educlass BaseCPU : public MemObject 742SN/A{ 751634SN/A protected: 761634SN/A // CPU's clock period in terms of the number of ticks of curTime. 771695SN/A Tick clock; 783814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 793814Ssaidi@eecs.umich.edu Tick instCnt; 801634SN/A 811634SN/A public: 822359SN/A// Tick currentTick; 831695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 841695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 851695SN/A inline Tick curCycle() const { return curTick / clock; } 863814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 873814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 881634SN/A 893495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 903495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 913495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 923495Sktlim@umich.edu */ 933495Sktlim@umich.edu Tick nextCycle(); 943495Sktlim@umich.edu 953495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 963495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 973495Sktlim@umich.edu * function may return curTick if the CPU should run on the 983495Sktlim@umich.edu * current cycle. 993495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1003495Sktlim@umich.edu */ 1013495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1023495Sktlim@umich.edu 1031858SN/A#if FULL_SYSTEM 1042SN/A protected: 1053520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1063520Sgblack@eecs.umich.edu// uint64_t intstatus; 1073520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1082SN/A 1092SN/A public: 1102SN/A virtual void post_interrupt(int int_num, int index); 1112SN/A virtual void clear_interrupt(int int_num, int index); 1122SN/A virtual void clear_interrupts(); 1134103Ssaidi@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1142SN/A 1153521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1163521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1171917SN/A 1181917SN/A class ProfileEvent : public Event 1191917SN/A { 1201917SN/A private: 1211917SN/A BaseCPU *cpu; 1221917SN/A int interval; 1231917SN/A 1241917SN/A public: 1251917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1261917SN/A void process(); 1271917SN/A }; 1281917SN/A ProfileEvent *profileEvent; 1292SN/A#endif 1302SN/A 1312SN/A protected: 1322680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1334182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1342SN/A 1352SN/A public: 136393SN/A 137393SN/A /// Notify the CPU that the indicated context is now active. The 138393SN/A /// delay parameter indicates the number of ticks to wait before 139393SN/A /// executing (typically 0 or 1). 140393SN/A virtual void activateContext(int thread_num, int delay) {} 141393SN/A 142393SN/A /// Notify the CPU that the indicated context is now suspended. 143393SN/A virtual void suspendContext(int thread_num) {} 144393SN/A 145393SN/A /// Notify the CPU that the indicated context is now deallocated. 146393SN/A virtual void deallocateContext(int thread_num) {} 147393SN/A 148393SN/A /// Notify the CPU that the indicated context is now halted. 149393SN/A virtual void haltContext(int thread_num) {} 1502SN/A 1514000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1524000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1534000Ssaidi@eecs.umich.edu 1544000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1554000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1564000Ssaidi@eecs.umich.edu 1572SN/A public: 1581400SN/A struct Params 1591400SN/A { 1601400SN/A std::string name; 1611400SN/A int numberOfThreads; 1621400SN/A bool deferRegistration; 1631400SN/A Counter max_insts_any_thread; 1641400SN/A Counter max_insts_all_threads; 1651400SN/A Counter max_loads_any_thread; 1661400SN/A Counter max_loads_all_threads; 1671695SN/A Tick clock; 1681400SN/A bool functionTrace; 1691400SN/A Tick functionTraceStart; 1702378SN/A System *system; 1713170Sstever@eecs.umich.edu int cpu_id; 1723661Srdreslin@umich.edu Tick phase; 1731858SN/A#if FULL_SYSTEM 1741917SN/A Tick profile; 1753617Sbinkertn@umich.edu 1763617Sbinkertn@umich.edu bool do_statistics_insts; 1773617Sbinkertn@umich.edu bool do_checkpoint_insts; 1783617Sbinkertn@umich.edu bool do_quiesce; 1791400SN/A#endif 1802356SN/A Tick progress_interval; 1812315SN/A BaseCPU *checker; 1821917SN/A 1831917SN/A Params(); 1841400SN/A }; 1852SN/A 1861400SN/A const Params *params; 1872SN/A 1881400SN/A BaseCPU(Params *params); 1891191SN/A virtual ~BaseCPU(); 1902SN/A 1911129SN/A virtual void init(); 1921917SN/A virtual void startup(); 1932SN/A virtual void regStats(); 1942SN/A 1952103SN/A virtual void activateWhenReady(int tid) {}; 1962103SN/A 1972680Sktlim@umich.edu void registerThreadContexts(); 198180SN/A 1991492SN/A /// Prepare for another CPU to take over execution. When it is 2001492SN/A /// is ready (drained pipe) it signals the sampler. 2012798Sktlim@umich.edu virtual void switchOut(); 202180SN/A 203180SN/A /// Take over execution from the given CPU. Used for warm-up and 204180SN/A /// sampling. 2054192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 206180SN/A 207124SN/A /** 208124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 209124SN/A * This is a constant for the duration of the simulation. 210124SN/A */ 2112SN/A int number_of_threads; 2122SN/A 213124SN/A /** 214124SN/A * Vector of per-thread instruction-based event queues. Used for 215124SN/A * scheduling events based on number of instructions committed by 216124SN/A * a particular thread. 217124SN/A */ 218503SN/A EventQueue **comInstEventQueue; 2192SN/A 220124SN/A /** 221124SN/A * Vector of per-thread load-based event queues. Used for 222124SN/A * scheduling events based on number of loads committed by 223124SN/A *a particular thread. 224124SN/A */ 225124SN/A EventQueue **comLoadEventQueue; 226124SN/A 2272SN/A System *system; 228921SN/A 2293661Srdreslin@umich.edu Tick phase; 2303661Srdreslin@umich.edu 2312378SN/A#if FULL_SYSTEM 232921SN/A /** 233921SN/A * Serialize this object to the given output stream. 234921SN/A * @param os The stream to serialize to. 235921SN/A */ 236921SN/A virtual void serialize(std::ostream &os); 237921SN/A 238921SN/A /** 239921SN/A * Reconstruct the state of this object from a checkpoint. 240921SN/A * @param cp The checkpoint use. 241921SN/A * @param section The section name of this object 242921SN/A */ 243921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 244921SN/A 2452SN/A#endif 2462SN/A 247124SN/A /** 248124SN/A * Return pointer to CPU's branch predictor (NULL if none). 249124SN/A * @return Branch predictor pointer. 250124SN/A */ 2512SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2522SN/A 253707SN/A virtual Counter totalInstructions() const { return 0; } 254707SN/A 2551191SN/A // Function tracing 2561191SN/A private: 2571191SN/A bool functionTracingEnabled; 2581191SN/A std::ostream *functionTraceStream; 2591191SN/A Addr currentFunctionStart; 2601191SN/A Addr currentFunctionEnd; 2611191SN/A Tick functionEntryTick; 2621191SN/A void enableFunctionTrace(); 2631191SN/A void traceFunctionsInternal(Addr pc); 2641191SN/A 2651191SN/A protected: 2661191SN/A void traceFunctions(Addr pc) 2671191SN/A { 2681191SN/A if (functionTracingEnabled) 2691191SN/A traceFunctionsInternal(pc); 2701191SN/A } 2711191SN/A 2722SN/A private: 2732SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2742SN/A 2752SN/A public: 2762SN/A static int numSimulatedCPUs() { return cpuList.size(); } 277707SN/A static Counter numSimulatedInstructions() 278707SN/A { 279707SN/A Counter total = 0; 280707SN/A 281707SN/A int size = cpuList.size(); 282707SN/A for (int i = 0; i < size; ++i) 283707SN/A total += cpuList[i]->totalInstructions(); 284707SN/A 285707SN/A return total; 286707SN/A } 287707SN/A 288707SN/A public: 289707SN/A // Number of CPU cycles simulated 290729SN/A Stats::Scalar<> numCycles; 2912SN/A}; 2922SN/A 2931717SN/A#endif // __CPU_BASE_HH__ 294