base.hh revision 3894
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 37707SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 3956SN/A#include "sim/eventq.hh" 402856Srdreslin@umich.edu#include "mem/mem_object.hh" 412109SN/A#include "arch/isa_traits.hh" 422SN/A 433520Sgblack@eecs.umich.edu#if FULL_SYSTEM 443520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 453520Sgblack@eecs.umich.edu#endif 463520Sgblack@eecs.umich.edu 472190SN/Aclass BranchPred; 482315SN/Aclass CheckerCPU; 492680Sktlim@umich.educlass ThreadContext; 502SN/Aclass System; 512856Srdreslin@umich.educlass Port; 522SN/A 532356SN/Aclass CPUProgressEvent : public Event 542356SN/A{ 552356SN/A protected: 562356SN/A Tick interval; 572356SN/A Counter lastNumInst; 582356SN/A BaseCPU *cpu; 592356SN/A 602356SN/A public: 613126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 622356SN/A 632356SN/A void process(); 642356SN/A 652356SN/A virtual const char *description(); 662356SN/A}; 672356SN/A 682856Srdreslin@umich.educlass BaseCPU : public MemObject 692SN/A{ 701634SN/A protected: 711634SN/A // CPU's clock period in terms of the number of ticks of curTime. 721695SN/A Tick clock; 733814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 743814Ssaidi@eecs.umich.edu Tick instCnt; 751634SN/A 761634SN/A public: 772359SN/A// Tick currentTick; 781695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 791695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 801695SN/A inline Tick curCycle() const { return curTick / clock; } 813814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 823814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 831634SN/A 843495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 853495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 863495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 873495Sktlim@umich.edu */ 883495Sktlim@umich.edu Tick nextCycle(); 893495Sktlim@umich.edu 903495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 913495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 923495Sktlim@umich.edu * function may return curTick if the CPU should run on the 933495Sktlim@umich.edu * current cycle. 943495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 953495Sktlim@umich.edu */ 963495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 973495Sktlim@umich.edu 981858SN/A#if FULL_SYSTEM 992SN/A protected: 1003520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1013520Sgblack@eecs.umich.edu// uint64_t intstatus; 1023520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1032SN/A 1042SN/A public: 1053894Shsul@eecs.umich.edu virtual void post_interrupt(int int_type); 1062SN/A virtual void post_interrupt(int int_num, int index); 1072SN/A virtual void clear_interrupt(int int_num, int index); 1082SN/A virtual void clear_interrupts(); 1091133SN/A bool checkInterrupts; 1102SN/A 1113521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1123521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1131917SN/A 1141917SN/A class ProfileEvent : public Event 1151917SN/A { 1161917SN/A private: 1171917SN/A BaseCPU *cpu; 1181917SN/A int interval; 1191917SN/A 1201917SN/A public: 1211917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1221917SN/A void process(); 1231917SN/A }; 1241917SN/A ProfileEvent *profileEvent; 1252SN/A#endif 1262SN/A 1272SN/A protected: 1282680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1292SN/A 1302SN/A public: 131393SN/A 132393SN/A /// Notify the CPU that the indicated context is now active. The 133393SN/A /// delay parameter indicates the number of ticks to wait before 134393SN/A /// executing (typically 0 or 1). 135393SN/A virtual void activateContext(int thread_num, int delay) {} 136393SN/A 137393SN/A /// Notify the CPU that the indicated context is now suspended. 138393SN/A virtual void suspendContext(int thread_num) {} 139393SN/A 140393SN/A /// Notify the CPU that the indicated context is now deallocated. 141393SN/A virtual void deallocateContext(int thread_num) {} 142393SN/A 143393SN/A /// Notify the CPU that the indicated context is now halted. 144393SN/A virtual void haltContext(int thread_num) {} 1452SN/A 1462SN/A public: 1471400SN/A struct Params 1481400SN/A { 1491400SN/A std::string name; 1501400SN/A int numberOfThreads; 1511400SN/A bool deferRegistration; 1521400SN/A Counter max_insts_any_thread; 1531400SN/A Counter max_insts_all_threads; 1541400SN/A Counter max_loads_any_thread; 1551400SN/A Counter max_loads_all_threads; 1561695SN/A Tick clock; 1571400SN/A bool functionTrace; 1581400SN/A Tick functionTraceStart; 1592378SN/A System *system; 1603170Sstever@eecs.umich.edu int cpu_id; 1613661Srdreslin@umich.edu Tick phase; 1621858SN/A#if FULL_SYSTEM 1631917SN/A Tick profile; 1643617Sbinkertn@umich.edu 1653617Sbinkertn@umich.edu bool do_statistics_insts; 1663617Sbinkertn@umich.edu bool do_checkpoint_insts; 1673617Sbinkertn@umich.edu bool do_quiesce; 1681400SN/A#endif 1692356SN/A Tick progress_interval; 1702315SN/A BaseCPU *checker; 1711917SN/A 1721917SN/A Params(); 1731400SN/A }; 1742SN/A 1751400SN/A const Params *params; 1762SN/A 1771400SN/A BaseCPU(Params *params); 1781191SN/A virtual ~BaseCPU(); 1792SN/A 1801129SN/A virtual void init(); 1811917SN/A virtual void startup(); 1822SN/A virtual void regStats(); 1832SN/A 1842103SN/A virtual void activateWhenReady(int tid) {}; 1852103SN/A 1862680Sktlim@umich.edu void registerThreadContexts(); 187180SN/A 1881492SN/A /// Prepare for another CPU to take over execution. When it is 1891492SN/A /// is ready (drained pipe) it signals the sampler. 1902798Sktlim@umich.edu virtual void switchOut(); 191180SN/A 192180SN/A /// Take over execution from the given CPU. Used for warm-up and 193180SN/A /// sampling. 194180SN/A virtual void takeOverFrom(BaseCPU *); 195180SN/A 196124SN/A /** 197124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 198124SN/A * This is a constant for the duration of the simulation. 199124SN/A */ 2002SN/A int number_of_threads; 2012SN/A 202124SN/A /** 203124SN/A * Vector of per-thread instruction-based event queues. Used for 204124SN/A * scheduling events based on number of instructions committed by 205124SN/A * a particular thread. 206124SN/A */ 207503SN/A EventQueue **comInstEventQueue; 2082SN/A 209124SN/A /** 210124SN/A * Vector of per-thread load-based event queues. Used for 211124SN/A * scheduling events based on number of loads committed by 212124SN/A *a particular thread. 213124SN/A */ 214124SN/A EventQueue **comLoadEventQueue; 215124SN/A 2162SN/A System *system; 217921SN/A 2183661Srdreslin@umich.edu Tick phase; 2193661Srdreslin@umich.edu 2202378SN/A#if FULL_SYSTEM 221921SN/A /** 222921SN/A * Serialize this object to the given output stream. 223921SN/A * @param os The stream to serialize to. 224921SN/A */ 225921SN/A virtual void serialize(std::ostream &os); 226921SN/A 227921SN/A /** 228921SN/A * Reconstruct the state of this object from a checkpoint. 229921SN/A * @param cp The checkpoint use. 230921SN/A * @param section The section name of this object 231921SN/A */ 232921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 233921SN/A 2342SN/A#endif 2352SN/A 236124SN/A /** 237124SN/A * Return pointer to CPU's branch predictor (NULL if none). 238124SN/A * @return Branch predictor pointer. 239124SN/A */ 2402SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2412SN/A 242707SN/A virtual Counter totalInstructions() const { return 0; } 243707SN/A 2441191SN/A // Function tracing 2451191SN/A private: 2461191SN/A bool functionTracingEnabled; 2471191SN/A std::ostream *functionTraceStream; 2481191SN/A Addr currentFunctionStart; 2491191SN/A Addr currentFunctionEnd; 2501191SN/A Tick functionEntryTick; 2511191SN/A void enableFunctionTrace(); 2521191SN/A void traceFunctionsInternal(Addr pc); 2531191SN/A 2541191SN/A protected: 2551191SN/A void traceFunctions(Addr pc) 2561191SN/A { 2571191SN/A if (functionTracingEnabled) 2581191SN/A traceFunctionsInternal(pc); 2591191SN/A } 2601191SN/A 2612SN/A private: 2622SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2632SN/A 2642SN/A public: 2652SN/A static int numSimulatedCPUs() { return cpuList.size(); } 266707SN/A static Counter numSimulatedInstructions() 267707SN/A { 268707SN/A Counter total = 0; 269707SN/A 270707SN/A int size = cpuList.size(); 271707SN/A for (int i = 0; i < size; ++i) 272707SN/A total += cpuList[i]->totalInstructions(); 273707SN/A 274707SN/A return total; 275707SN/A } 276707SN/A 277707SN/A public: 278707SN/A // Number of CPU cycles simulated 279729SN/A Stats::Scalar<> numCycles; 2802SN/A}; 2812SN/A 2821717SN/A#endif // __CPU_BASE_HH__ 283