base.hh revision 3495
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 37707SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 3956SN/A#include "sim/eventq.hh" 402856Srdreslin@umich.edu#include "mem/mem_object.hh" 412109SN/A#include "arch/isa_traits.hh" 422SN/A 432190SN/Aclass BranchPred; 442315SN/Aclass CheckerCPU; 452680Sktlim@umich.educlass ThreadContext; 462SN/Aclass System; 472856Srdreslin@umich.educlass Port; 482SN/A 492356SN/Aclass CPUProgressEvent : public Event 502356SN/A{ 512356SN/A protected: 522356SN/A Tick interval; 532356SN/A Counter lastNumInst; 542356SN/A BaseCPU *cpu; 552356SN/A 562356SN/A public: 573126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 582356SN/A 592356SN/A void process(); 602356SN/A 612356SN/A virtual const char *description(); 622356SN/A}; 632356SN/A 642856Srdreslin@umich.educlass BaseCPU : public MemObject 652SN/A{ 661634SN/A protected: 671634SN/A // CPU's clock period in terms of the number of ticks of curTime. 681695SN/A Tick clock; 691634SN/A 701634SN/A public: 712359SN/A// Tick currentTick; 721695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 731695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 741695SN/A inline Tick curCycle() const { return curTick / clock; } 751634SN/A 763495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 773495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 783495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 793495Sktlim@umich.edu */ 803495Sktlim@umich.edu Tick nextCycle(); 813495Sktlim@umich.edu 823495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 833495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 843495Sktlim@umich.edu * function may return curTick if the CPU should run on the 853495Sktlim@umich.edu * current cycle. 863495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 873495Sktlim@umich.edu */ 883495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 893495Sktlim@umich.edu 901858SN/A#if FULL_SYSTEM 912SN/A protected: 922107SN/A uint64_t interrupts[TheISA::NumInterruptLevels]; 932SN/A uint64_t intstatus; 942SN/A 952SN/A public: 962SN/A virtual void post_interrupt(int int_num, int index); 972SN/A virtual void clear_interrupt(int int_num, int index); 982SN/A virtual void clear_interrupts(); 991133SN/A bool checkInterrupts; 1002SN/A 1012SN/A bool check_interrupt(int int_num) const { 1022107SN/A if (int_num > TheISA::NumInterruptLevels) 1032SN/A panic("int_num out of bounds\n"); 1042SN/A 1052SN/A return interrupts[int_num] != 0; 1062SN/A } 1072SN/A 1082SN/A bool check_interrupts() const { return intstatus != 0; } 1092SN/A uint64_t intr_status() const { return intstatus; } 1101917SN/A 1111917SN/A class ProfileEvent : public Event 1121917SN/A { 1131917SN/A private: 1141917SN/A BaseCPU *cpu; 1151917SN/A int interval; 1161917SN/A 1171917SN/A public: 1181917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1191917SN/A void process(); 1201917SN/A }; 1211917SN/A ProfileEvent *profileEvent; 1222SN/A#endif 1232SN/A 1242SN/A protected: 1252680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1262SN/A 1272SN/A public: 128393SN/A 129393SN/A /// Notify the CPU that the indicated context is now active. The 130393SN/A /// delay parameter indicates the number of ticks to wait before 131393SN/A /// executing (typically 0 or 1). 132393SN/A virtual void activateContext(int thread_num, int delay) {} 133393SN/A 134393SN/A /// Notify the CPU that the indicated context is now suspended. 135393SN/A virtual void suspendContext(int thread_num) {} 136393SN/A 137393SN/A /// Notify the CPU that the indicated context is now deallocated. 138393SN/A virtual void deallocateContext(int thread_num) {} 139393SN/A 140393SN/A /// Notify the CPU that the indicated context is now halted. 141393SN/A virtual void haltContext(int thread_num) {} 1422SN/A 1432SN/A public: 1441400SN/A struct Params 1451400SN/A { 1461400SN/A std::string name; 1471400SN/A int numberOfThreads; 1481400SN/A bool deferRegistration; 1491400SN/A Counter max_insts_any_thread; 1501400SN/A Counter max_insts_all_threads; 1511400SN/A Counter max_loads_any_thread; 1521400SN/A Counter max_loads_all_threads; 1531695SN/A Tick clock; 1541400SN/A bool functionTrace; 1551400SN/A Tick functionTraceStart; 1562378SN/A System *system; 1573170Sstever@eecs.umich.edu int cpu_id; 1581858SN/A#if FULL_SYSTEM 1591917SN/A Tick profile; 1601400SN/A#endif 1612356SN/A Tick progress_interval; 1622315SN/A BaseCPU *checker; 1631917SN/A 1641917SN/A Params(); 1651400SN/A }; 1662SN/A 1671400SN/A const Params *params; 1682SN/A 1691400SN/A BaseCPU(Params *params); 1701191SN/A virtual ~BaseCPU(); 1712SN/A 1721129SN/A virtual void init(); 1731917SN/A virtual void startup(); 1742SN/A virtual void regStats(); 1752SN/A 1762103SN/A virtual void activateWhenReady(int tid) {}; 1772103SN/A 1782680Sktlim@umich.edu void registerThreadContexts(); 179180SN/A 1801492SN/A /// Prepare for another CPU to take over execution. When it is 1811492SN/A /// is ready (drained pipe) it signals the sampler. 1822798Sktlim@umich.edu virtual void switchOut(); 183180SN/A 184180SN/A /// Take over execution from the given CPU. Used for warm-up and 185180SN/A /// sampling. 186180SN/A virtual void takeOverFrom(BaseCPU *); 187180SN/A 188124SN/A /** 189124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 190124SN/A * This is a constant for the duration of the simulation. 191124SN/A */ 1922SN/A int number_of_threads; 1932SN/A 194124SN/A /** 195124SN/A * Vector of per-thread instruction-based event queues. Used for 196124SN/A * scheduling events based on number of instructions committed by 197124SN/A * a particular thread. 198124SN/A */ 199503SN/A EventQueue **comInstEventQueue; 2002SN/A 201124SN/A /** 202124SN/A * Vector of per-thread load-based event queues. Used for 203124SN/A * scheduling events based on number of loads committed by 204124SN/A *a particular thread. 205124SN/A */ 206124SN/A EventQueue **comLoadEventQueue; 207124SN/A 2082SN/A System *system; 209921SN/A 2102378SN/A#if FULL_SYSTEM 211921SN/A /** 212921SN/A * Serialize this object to the given output stream. 213921SN/A * @param os The stream to serialize to. 214921SN/A */ 215921SN/A virtual void serialize(std::ostream &os); 216921SN/A 217921SN/A /** 218921SN/A * Reconstruct the state of this object from a checkpoint. 219921SN/A * @param cp The checkpoint use. 220921SN/A * @param section The section name of this object 221921SN/A */ 222921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 223921SN/A 2242SN/A#endif 2252SN/A 226124SN/A /** 227124SN/A * Return pointer to CPU's branch predictor (NULL if none). 228124SN/A * @return Branch predictor pointer. 229124SN/A */ 2302SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2312SN/A 232707SN/A virtual Counter totalInstructions() const { return 0; } 233707SN/A 2341191SN/A // Function tracing 2351191SN/A private: 2361191SN/A bool functionTracingEnabled; 2371191SN/A std::ostream *functionTraceStream; 2381191SN/A Addr currentFunctionStart; 2391191SN/A Addr currentFunctionEnd; 2401191SN/A Tick functionEntryTick; 2411191SN/A void enableFunctionTrace(); 2421191SN/A void traceFunctionsInternal(Addr pc); 2431191SN/A 2441191SN/A protected: 2451191SN/A void traceFunctions(Addr pc) 2461191SN/A { 2471191SN/A if (functionTracingEnabled) 2481191SN/A traceFunctionsInternal(pc); 2491191SN/A } 2501191SN/A 2512SN/A private: 2522SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2532SN/A 2542SN/A public: 2552SN/A static int numSimulatedCPUs() { return cpuList.size(); } 256707SN/A static Counter numSimulatedInstructions() 257707SN/A { 258707SN/A Counter total = 0; 259707SN/A 260707SN/A int size = cpuList.size(); 261707SN/A for (int i = 0; i < size; ++i) 262707SN/A total += cpuList[i]->totalInstructions(); 263707SN/A 264707SN/A return total; 265707SN/A } 266707SN/A 267707SN/A public: 268707SN/A // Number of CPU cycles simulated 269729SN/A Stats::Scalar<> numCycles; 2702SN/A}; 2712SN/A 2721717SN/A#endif // __CPU_BASE_HH__ 273