base.hh revision 3126
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 37707SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 3956SN/A#include "sim/eventq.hh" 402856Srdreslin@umich.edu#include "mem/mem_object.hh" 412109SN/A#include "arch/isa_traits.hh" 422SN/A 432190SN/Aclass BranchPred; 442315SN/Aclass CheckerCPU; 452680Sktlim@umich.educlass ThreadContext; 462SN/Aclass System; 472856Srdreslin@umich.educlass Port; 482SN/A 492356SN/Aclass CPUProgressEvent : public Event 502356SN/A{ 512356SN/A protected: 522356SN/A Tick interval; 532356SN/A Counter lastNumInst; 542356SN/A BaseCPU *cpu; 552356SN/A 562356SN/A public: 573126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 582356SN/A 592356SN/A void process(); 602356SN/A 612356SN/A virtual const char *description(); 622356SN/A}; 632356SN/A 642856Srdreslin@umich.educlass BaseCPU : public MemObject 652SN/A{ 661634SN/A protected: 671634SN/A // CPU's clock period in terms of the number of ticks of curTime. 681695SN/A Tick clock; 691634SN/A 701634SN/A public: 712359SN/A// Tick currentTick; 721695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 731695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 741695SN/A inline Tick curCycle() const { return curTick / clock; } 751634SN/A 761858SN/A#if FULL_SYSTEM 772SN/A protected: 782107SN/A uint64_t interrupts[TheISA::NumInterruptLevels]; 792SN/A uint64_t intstatus; 802SN/A 812SN/A public: 822SN/A virtual void post_interrupt(int int_num, int index); 832SN/A virtual void clear_interrupt(int int_num, int index); 842SN/A virtual void clear_interrupts(); 851133SN/A bool checkInterrupts; 862SN/A 872SN/A bool check_interrupt(int int_num) const { 882107SN/A if (int_num > TheISA::NumInterruptLevels) 892SN/A panic("int_num out of bounds\n"); 902SN/A 912SN/A return interrupts[int_num] != 0; 922SN/A } 932SN/A 942SN/A bool check_interrupts() const { return intstatus != 0; } 952SN/A uint64_t intr_status() const { return intstatus; } 961917SN/A 971917SN/A class ProfileEvent : public Event 981917SN/A { 991917SN/A private: 1001917SN/A BaseCPU *cpu; 1011917SN/A int interval; 1021917SN/A 1031917SN/A public: 1041917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1051917SN/A void process(); 1061917SN/A }; 1071917SN/A ProfileEvent *profileEvent; 1082SN/A#endif 1092SN/A 1102SN/A protected: 1112680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1122SN/A 1132SN/A public: 114393SN/A 115393SN/A /// Notify the CPU that the indicated context is now active. The 116393SN/A /// delay parameter indicates the number of ticks to wait before 117393SN/A /// executing (typically 0 or 1). 118393SN/A virtual void activateContext(int thread_num, int delay) {} 119393SN/A 120393SN/A /// Notify the CPU that the indicated context is now suspended. 121393SN/A virtual void suspendContext(int thread_num) {} 122393SN/A 123393SN/A /// Notify the CPU that the indicated context is now deallocated. 124393SN/A virtual void deallocateContext(int thread_num) {} 125393SN/A 126393SN/A /// Notify the CPU that the indicated context is now halted. 127393SN/A virtual void haltContext(int thread_num) {} 1282SN/A 1292SN/A public: 1301400SN/A struct Params 1311400SN/A { 1321400SN/A std::string name; 1331400SN/A int numberOfThreads; 1341400SN/A bool deferRegistration; 1351400SN/A Counter max_insts_any_thread; 1361400SN/A Counter max_insts_all_threads; 1371400SN/A Counter max_loads_any_thread; 1381400SN/A Counter max_loads_all_threads; 1391695SN/A Tick clock; 1401400SN/A bool functionTrace; 1411400SN/A Tick functionTraceStart; 1422378SN/A System *system; 1431858SN/A#if FULL_SYSTEM 1441806SN/A int cpu_id; 1451917SN/A Tick profile; 1461400SN/A#endif 1472356SN/A Tick progress_interval; 1482315SN/A BaseCPU *checker; 1491917SN/A 1501917SN/A Params(); 1511400SN/A }; 1522SN/A 1531400SN/A const Params *params; 1542SN/A 1551400SN/A BaseCPU(Params *params); 1561191SN/A virtual ~BaseCPU(); 1572SN/A 1581129SN/A virtual void init(); 1591917SN/A virtual void startup(); 1602SN/A virtual void regStats(); 1612SN/A 1622103SN/A virtual void activateWhenReady(int tid) {}; 1632103SN/A 1642680Sktlim@umich.edu void registerThreadContexts(); 165180SN/A 1661492SN/A /// Prepare for another CPU to take over execution. When it is 1671492SN/A /// is ready (drained pipe) it signals the sampler. 1682798Sktlim@umich.edu virtual void switchOut(); 169180SN/A 170180SN/A /// Take over execution from the given CPU. Used for warm-up and 171180SN/A /// sampling. 172180SN/A virtual void takeOverFrom(BaseCPU *); 173180SN/A 174124SN/A /** 175124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 176124SN/A * This is a constant for the duration of the simulation. 177124SN/A */ 1782SN/A int number_of_threads; 1792SN/A 180124SN/A /** 181124SN/A * Vector of per-thread instruction-based event queues. Used for 182124SN/A * scheduling events based on number of instructions committed by 183124SN/A * a particular thread. 184124SN/A */ 185503SN/A EventQueue **comInstEventQueue; 1862SN/A 187124SN/A /** 188124SN/A * Vector of per-thread load-based event queues. Used for 189124SN/A * scheduling events based on number of loads committed by 190124SN/A *a particular thread. 191124SN/A */ 192124SN/A EventQueue **comLoadEventQueue; 193124SN/A 1942SN/A System *system; 195921SN/A 1962378SN/A#if FULL_SYSTEM 197921SN/A /** 198921SN/A * Serialize this object to the given output stream. 199921SN/A * @param os The stream to serialize to. 200921SN/A */ 201921SN/A virtual void serialize(std::ostream &os); 202921SN/A 203921SN/A /** 204921SN/A * Reconstruct the state of this object from a checkpoint. 205921SN/A * @param cp The checkpoint use. 206921SN/A * @param section The section name of this object 207921SN/A */ 208921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 209921SN/A 2102SN/A#endif 2112SN/A 212124SN/A /** 213124SN/A * Return pointer to CPU's branch predictor (NULL if none). 214124SN/A * @return Branch predictor pointer. 215124SN/A */ 2162SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2172SN/A 218707SN/A virtual Counter totalInstructions() const { return 0; } 219707SN/A 2201191SN/A // Function tracing 2211191SN/A private: 2221191SN/A bool functionTracingEnabled; 2231191SN/A std::ostream *functionTraceStream; 2241191SN/A Addr currentFunctionStart; 2251191SN/A Addr currentFunctionEnd; 2261191SN/A Tick functionEntryTick; 2271191SN/A void enableFunctionTrace(); 2281191SN/A void traceFunctionsInternal(Addr pc); 2291191SN/A 2301191SN/A protected: 2311191SN/A void traceFunctions(Addr pc) 2321191SN/A { 2331191SN/A if (functionTracingEnabled) 2341191SN/A traceFunctionsInternal(pc); 2351191SN/A } 2361191SN/A 2372SN/A private: 2382SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2392SN/A 2402SN/A public: 2412SN/A static int numSimulatedCPUs() { return cpuList.size(); } 242707SN/A static Counter numSimulatedInstructions() 243707SN/A { 244707SN/A Counter total = 0; 245707SN/A 246707SN/A int size = cpuList.size(); 247707SN/A for (int i = 0; i < size; ++i) 248707SN/A total += cpuList[i]->totalInstructions(); 249707SN/A 250707SN/A return total; 251707SN/A } 252707SN/A 253707SN/A public: 254707SN/A // Number of CPU cycles simulated 255729SN/A Stats::Scalar<> numCycles; 2562SN/A}; 2572SN/A 2581717SN/A#endif // __CPU_BASE_HH__ 259