base.hh revision 2856
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 37707SN/A#include "base/statistics.hh" 381858SN/A#include "config/full_system.hh" 3956SN/A#include "sim/eventq.hh" 402856Srdreslin@umich.edu#include "mem/mem_object.hh" 412109SN/A#include "arch/isa_traits.hh" 422SN/A 432190SN/Aclass BranchPred; 442315SN/Aclass CheckerCPU; 452680Sktlim@umich.educlass ThreadContext; 462SN/Aclass System; 472856Srdreslin@umich.educlass Port; 482SN/A 492856Srdreslin@umich.educlass BaseCPU : public MemObject 502SN/A{ 511634SN/A protected: 521634SN/A // CPU's clock period in terms of the number of ticks of curTime. 531695SN/A Tick clock; 541634SN/A 551634SN/A public: 561695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 571695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 581695SN/A inline Tick curCycle() const { return curTick / clock; } 591634SN/A 601858SN/A#if FULL_SYSTEM 612SN/A protected: 622107SN/A uint64_t interrupts[TheISA::NumInterruptLevels]; 632SN/A uint64_t intstatus; 642SN/A 652SN/A public: 662SN/A virtual void post_interrupt(int int_num, int index); 672SN/A virtual void clear_interrupt(int int_num, int index); 682SN/A virtual void clear_interrupts(); 691133SN/A bool checkInterrupts; 702SN/A 712SN/A bool check_interrupt(int int_num) const { 722107SN/A if (int_num > TheISA::NumInterruptLevels) 732SN/A panic("int_num out of bounds\n"); 742SN/A 752SN/A return interrupts[int_num] != 0; 762SN/A } 772SN/A 782SN/A bool check_interrupts() const { return intstatus != 0; } 792SN/A uint64_t intr_status() const { return intstatus; } 801917SN/A 811917SN/A class ProfileEvent : public Event 821917SN/A { 831917SN/A private: 841917SN/A BaseCPU *cpu; 851917SN/A int interval; 861917SN/A 871917SN/A public: 881917SN/A ProfileEvent(BaseCPU *cpu, int interval); 891917SN/A void process(); 901917SN/A }; 911917SN/A ProfileEvent *profileEvent; 922SN/A#endif 932SN/A 942SN/A protected: 952680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 962SN/A 972SN/A public: 98393SN/A 99393SN/A /// Notify the CPU that the indicated context is now active. The 100393SN/A /// delay parameter indicates the number of ticks to wait before 101393SN/A /// executing (typically 0 or 1). 102393SN/A virtual void activateContext(int thread_num, int delay) {} 103393SN/A 104393SN/A /// Notify the CPU that the indicated context is now suspended. 105393SN/A virtual void suspendContext(int thread_num) {} 106393SN/A 107393SN/A /// Notify the CPU that the indicated context is now deallocated. 108393SN/A virtual void deallocateContext(int thread_num) {} 109393SN/A 110393SN/A /// Notify the CPU that the indicated context is now halted. 111393SN/A virtual void haltContext(int thread_num) {} 1122SN/A 1132SN/A public: 1141400SN/A struct Params 1151400SN/A { 1161400SN/A std::string name; 1171400SN/A int numberOfThreads; 1181400SN/A bool deferRegistration; 1191400SN/A Counter max_insts_any_thread; 1201400SN/A Counter max_insts_all_threads; 1211400SN/A Counter max_loads_any_thread; 1221400SN/A Counter max_loads_all_threads; 1231695SN/A Tick clock; 1241400SN/A bool functionTrace; 1251400SN/A Tick functionTraceStart; 1262378SN/A System *system; 1271858SN/A#if FULL_SYSTEM 1281806SN/A int cpu_id; 1291917SN/A Tick profile; 1301400SN/A#endif 1312315SN/A BaseCPU *checker; 1321917SN/A 1331917SN/A Params(); 1341400SN/A }; 1352SN/A 1361400SN/A const Params *params; 1372SN/A 1381400SN/A BaseCPU(Params *params); 1391191SN/A virtual ~BaseCPU(); 1402SN/A 1411129SN/A virtual void init(); 1421917SN/A virtual void startup(); 1432SN/A virtual void regStats(); 1442SN/A 1452103SN/A virtual void activateWhenReady(int tid) {}; 1462103SN/A 1472680Sktlim@umich.edu void registerThreadContexts(); 148180SN/A 1491492SN/A /// Prepare for another CPU to take over execution. When it is 1501492SN/A /// is ready (drained pipe) it signals the sampler. 1512798Sktlim@umich.edu virtual void switchOut(); 152180SN/A 153180SN/A /// Take over execution from the given CPU. Used for warm-up and 154180SN/A /// sampling. 155180SN/A virtual void takeOverFrom(BaseCPU *); 156180SN/A 157124SN/A /** 158124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 159124SN/A * This is a constant for the duration of the simulation. 160124SN/A */ 1612SN/A int number_of_threads; 1622SN/A 163124SN/A /** 164124SN/A * Vector of per-thread instruction-based event queues. Used for 165124SN/A * scheduling events based on number of instructions committed by 166124SN/A * a particular thread. 167124SN/A */ 168503SN/A EventQueue **comInstEventQueue; 1692SN/A 170124SN/A /** 171124SN/A * Vector of per-thread load-based event queues. Used for 172124SN/A * scheduling events based on number of loads committed by 173124SN/A *a particular thread. 174124SN/A */ 175124SN/A EventQueue **comLoadEventQueue; 176124SN/A 1772SN/A System *system; 178921SN/A 1792378SN/A#if FULL_SYSTEM 180921SN/A /** 181921SN/A * Serialize this object to the given output stream. 182921SN/A * @param os The stream to serialize to. 183921SN/A */ 184921SN/A virtual void serialize(std::ostream &os); 185921SN/A 186921SN/A /** 187921SN/A * Reconstruct the state of this object from a checkpoint. 188921SN/A * @param cp The checkpoint use. 189921SN/A * @param section The section name of this object 190921SN/A */ 191921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 192921SN/A 1932SN/A#endif 1942SN/A 195124SN/A /** 196124SN/A * Return pointer to CPU's branch predictor (NULL if none). 197124SN/A * @return Branch predictor pointer. 198124SN/A */ 1992SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2002SN/A 201707SN/A virtual Counter totalInstructions() const { return 0; } 202707SN/A 2031191SN/A // Function tracing 2041191SN/A private: 2051191SN/A bool functionTracingEnabled; 2061191SN/A std::ostream *functionTraceStream; 2071191SN/A Addr currentFunctionStart; 2081191SN/A Addr currentFunctionEnd; 2091191SN/A Tick functionEntryTick; 2101191SN/A void enableFunctionTrace(); 2111191SN/A void traceFunctionsInternal(Addr pc); 2121191SN/A 2131191SN/A protected: 2141191SN/A void traceFunctions(Addr pc) 2151191SN/A { 2161191SN/A if (functionTracingEnabled) 2171191SN/A traceFunctionsInternal(pc); 2181191SN/A } 2191191SN/A 2202SN/A private: 2212SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2222SN/A 2232SN/A public: 2242SN/A static int numSimulatedCPUs() { return cpuList.size(); } 225707SN/A static Counter numSimulatedInstructions() 226707SN/A { 227707SN/A Counter total = 0; 228707SN/A 229707SN/A int size = cpuList.size(); 230707SN/A for (int i = 0; i < size; ++i) 231707SN/A total += cpuList[i]->totalInstructions(); 232707SN/A 233707SN/A return total; 234707SN/A } 235707SN/A 236707SN/A public: 237707SN/A // Number of CPU cycles simulated 238729SN/A Stats::Scalar<> numCycles; 2392SN/A}; 2402SN/A 2411717SN/A#endif // __CPU_BASE_HH__ 242