base.hh revision 2356
12SN/A/* 211071SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 311071SN/A * All rights reserved. 411071SN/A * 511071SN/A * Redistribution and use in source and binary forms, with or without 611071SN/A * modification, are permitted provided that the following conditions are 711071SN/A * met: redistributions of source code must retain the above copyright 811071SN/A * notice, this list of conditions and the following disclaimer; 911071SN/A * redistributions in binary form must reproduce the above copyright 1011071SN/A * notice, this list of conditions and the following disclaimer in the 1111071SN/A * documentation and/or other materials provided with the distribution; 1211071SN/A * neither the name of the copyright holders nor the names of its 1311071SN/A * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#ifndef __CPU_BASE_HH__ 302SN/A#define __CPU_BASE_HH__ 312SN/A 322SN/A#include <vector> 332SN/A 342SN/A#include "base/statistics.hh" 352SN/A#include "config/full_system.hh" 362SN/A#include "cpu/sampler/sampler.hh" 372SN/A#include "sim/eventq.hh" 382SN/A#include "sim/sim_object.hh" 392665SN/A#include "arch/isa_traits.hh" 402665SN/A 412SN/Aclass BranchPred; 422SN/Aclass CheckerCPU; 432SN/Aclass ExecContext; 442SN/Aclass System; 452SN/A 462SN/Aclass CPUProgressEvent : public Event 4711263Sandreas.sandberg@arm.com{ 4811263Sandreas.sandberg@arm.com protected: 492SN/A Tick interval; 5011071SN/A Counter lastNumInst; 5111071SN/A BaseCPU *cpu; 526216SN/A 5311263Sandreas.sandberg@arm.com public: 5411263Sandreas.sandberg@arm.com CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu) 5511263Sandreas.sandberg@arm.com : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu) 564981SN/A { schedule(curTick + interval); } 571354SN/A 5856SN/A void process(); 592SN/A 602SN/A virtual const char *description(); 611435SN/A}; 622SN/A 632SN/Aclass BaseCPU : public SimObject 642SN/A{ 654981SN/A protected: 662SN/A // CPU's clock period in terms of the number of ticks of curTime. 672SN/A Tick clock; 682SN/A 692SN/A public: 7011071SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 7111071SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 7211071SN/A inline Tick curCycle() const { return curTick / clock; } 731435SN/A 741435SN/A#if FULL_SYSTEM 752SN/A protected: 7611071SN/A uint64_t interrupts[TheISA::NumInterruptLevels]; 77265SN/A uint64_t intstatus; 7811071SN/A 7911071SN/A public: 801435SN/A virtual void post_interrupt(int int_num, int index); 812SN/A virtual void clear_interrupt(int int_num, int index); 822SN/A virtual void clear_interrupts(); 832SN/A bool checkInterrupts; 8411071SN/A 8511071SN/A bool check_interrupt(int int_num) const { 8611071SN/A if (int_num > TheISA::NumInterruptLevels) 8711071SN/A panic("int_num out of bounds\n"); 882SN/A 892SN/A return interrupts[int_num] != 0; 902SN/A } 912SN/A 922SN/A bool check_interrupts() const { return intstatus != 0; } 932566SN/A uint64_t intr_status() const { return intstatus; } 94633SN/A 95633SN/A class ProfileEvent : public Event 961354SN/A { 97633SN/A private: 982SN/A BaseCPU *cpu; 9911071SN/A int interval; 10011071SN/A 10111071SN/A public: 10211071SN/A ProfileEvent(BaseCPU *cpu, int interval); 10311071SN/A void process(); 10411071SN/A }; 10511071SN/A ProfileEvent *profileEvent; 10611071SN/A#endif 10711071SN/A 10811071SN/A protected: 10911071SN/A std::vector<ExecContext *> execContexts; 11011071SN/A 1112566SN/A public: 1122SN/A 1132SN/A /// Notify the CPU that the indicated context is now active. The 1141435SN/A /// delay parameter indicates the number of ticks to wait before 1151954SN/A /// executing (typically 0 or 1). 1162SN/A virtual void activateContext(int thread_num, int delay) {} 1172SN/A 1181435SN/A /// Notify the CPU that the indicated context is now suspended. 119265SN/A virtual void suspendContext(int thread_num) {} 1202SN/A 1212566SN/A /// Notify the CPU that the indicated context is now deallocated. 1222SN/A virtual void deallocateContext(int thread_num) {} 1232SN/A 1242SN/A /// Notify the CPU that the indicated context is now halted. 125558SN/A virtual void haltContext(int thread_num) {} 12610905SN/A 12710905SN/A public: 1282SN/A struct Params 1292SN/A { 1302SN/A std::string name; 1312SN/A int numberOfThreads; 1322SN/A bool deferRegistration; 1332SN/A Counter max_insts_any_thread; 1342SN/A Counter max_insts_all_threads; 1352SN/A Counter max_loads_any_thread; 1362SN/A Counter max_loads_all_threads; 1372SN/A Tick clock; 1382SN/A bool functionTrace; 1392SN/A Tick functionTraceStart; 1402566SN/A#if FULL_SYSTEM 1411017SN/A System *system; 1424419SN/A int cpu_id; 1432SN/A Tick profile; 1442SN/A#endif 1451435SN/A Tick progress_interval; 1464981SN/A BaseCPU *checker; 1472SN/A 1482SN/A Params(); 1494981SN/A }; 1504981SN/A 1512SN/A const Params *params; 152558SN/A 1534981SN/A BaseCPU(Params *params); 1544981SN/A virtual ~BaseCPU(); 1554981SN/A 1564981SN/A virtual void init(); 1574981SN/A virtual void startup(); 1584981SN/A virtual void regStats(); 15911169SN/A 1604981SN/A virtual void activateWhenReady(int tid) {}; 16111168SN/A 16211168SN/A void registerExecContexts(); 163558SN/A 1642SN/A /// Prepare for another CPU to take over execution. When it is 1652SN/A /// is ready (drained pipe) it signals the sampler. 16611263Sandreas.sandberg@arm.com virtual void switchOut(Sampler *); 167 168 /// Take over execution from the given CPU. Used for warm-up and 169 /// sampling. 170 virtual void takeOverFrom(BaseCPU *); 171 172 /** 173 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 174 * This is a constant for the duration of the simulation. 175 */ 176 int number_of_threads; 177 178 /** 179 * Vector of per-thread instruction-based event queues. Used for 180 * scheduling events based on number of instructions committed by 181 * a particular thread. 182 */ 183 EventQueue **comInstEventQueue; 184 185 /** 186 * Vector of per-thread load-based event queues. Used for 187 * scheduling events based on number of loads committed by 188 *a particular thread. 189 */ 190 EventQueue **comLoadEventQueue; 191 192#if FULL_SYSTEM 193 System *system; 194 195 /** 196 * Serialize this object to the given output stream. 197 * @param os The stream to serialize to. 198 */ 199 virtual void serialize(std::ostream &os); 200 201 /** 202 * Reconstruct the state of this object from a checkpoint. 203 * @param cp The checkpoint use. 204 * @param section The section name of this object 205 */ 206 virtual void unserialize(Checkpoint *cp, const std::string §ion); 207 208#endif 209 210 /** 211 * Return pointer to CPU's branch predictor (NULL if none). 212 * @return Branch predictor pointer. 213 */ 214 virtual BranchPred *getBranchPred() { return NULL; }; 215 216 virtual Counter totalInstructions() const { return 0; } 217 218 // Function tracing 219 private: 220 bool functionTracingEnabled; 221 std::ostream *functionTraceStream; 222 Addr currentFunctionStart; 223 Addr currentFunctionEnd; 224 Tick functionEntryTick; 225 void enableFunctionTrace(); 226 void traceFunctionsInternal(Addr pc); 227 228 protected: 229 void traceFunctions(Addr pc) 230 { 231 if (functionTracingEnabled) 232 traceFunctionsInternal(pc); 233 } 234 235 private: 236 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 237 238 public: 239 static int numSimulatedCPUs() { return cpuList.size(); } 240 static Counter numSimulatedInstructions() 241 { 242 Counter total = 0; 243 244 int size = cpuList.size(); 245 for (int i = 0; i < size; ++i) 246 total += cpuList[i]->totalInstructions(); 247 248 return total; 249 } 250 251 public: 252 // Number of CPU cycles simulated 253 Stats::Scalar<> numCycles; 254}; 255 256#endif // __CPU_BASE_HH__ 257