base.hh revision 1858 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_BASE_HH__
30#define __CPU_BASE_HH__
31
32#include <vector>
33
34#include "base/statistics.hh"
35#include "config/full_system.hh"
36#include "cpu/sampler/sampler.hh"
37#include "sim/eventq.hh"
38#include "sim/sim_object.hh"
39#include "targetarch/isa_traits.hh"
40
41#if FULL_SYSTEM
42class System;
43#endif
44
45class BranchPred;
46class ExecContext;
47
48class BaseCPU : public SimObject
49{
50  protected:
51    // CPU's clock period in terms of the number of ticks of curTime.
52    Tick clock;
53
54  public:
55    inline Tick frequency() const { return Clock::Frequency / clock; }
56    inline Tick cycles(int numCycles) const { return clock * numCycles; }
57    inline Tick curCycle() const { return curTick / clock; }
58
59#if FULL_SYSTEM
60  protected:
61    uint64_t interrupts[NumInterruptLevels];
62    uint64_t intstatus;
63
64  public:
65    virtual void post_interrupt(int int_num, int index);
66    virtual void clear_interrupt(int int_num, int index);
67    virtual void clear_interrupts();
68    bool checkInterrupts;
69
70    bool check_interrupt(int int_num) const {
71        if (int_num > NumInterruptLevels)
72            panic("int_num out of bounds\n");
73
74        return interrupts[int_num] != 0;
75    }
76
77    bool check_interrupts() const { return intstatus != 0; }
78    uint64_t intr_status() const { return intstatus; }
79#endif
80
81  protected:
82    std::vector<ExecContext *> execContexts;
83
84  public:
85
86    /// Notify the CPU that the indicated context is now active.  The
87    /// delay parameter indicates the number of ticks to wait before
88    /// executing (typically 0 or 1).
89    virtual void activateContext(int thread_num, int delay) {}
90
91    /// Notify the CPU that the indicated context is now suspended.
92    virtual void suspendContext(int thread_num) {}
93
94    /// Notify the CPU that the indicated context is now deallocated.
95    virtual void deallocateContext(int thread_num) {}
96
97    /// Notify the CPU that the indicated context is now halted.
98    virtual void haltContext(int thread_num) {}
99
100  public:
101    struct Params
102    {
103        std::string name;
104        int numberOfThreads;
105        bool deferRegistration;
106        Counter max_insts_any_thread;
107        Counter max_insts_all_threads;
108        Counter max_loads_any_thread;
109        Counter max_loads_all_threads;
110        Tick clock;
111        bool functionTrace;
112        Tick functionTraceStart;
113#if FULL_SYSTEM
114        System *system;
115        int cpu_id;
116#endif
117    };
118
119    const Params *params;
120
121    BaseCPU(Params *params);
122    virtual ~BaseCPU();
123
124    virtual void init();
125    virtual void regStats();
126
127    void registerExecContexts();
128
129    /// Prepare for another CPU to take over execution.  When it is
130    /// is ready (drained pipe) it signals the sampler.
131    virtual void switchOut(Sampler *);
132
133    /// Take over execution from the given CPU.  Used for warm-up and
134    /// sampling.
135    virtual void takeOverFrom(BaseCPU *);
136
137    /**
138     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
139     * This is a constant for the duration of the simulation.
140     */
141    int number_of_threads;
142
143    /**
144     * Vector of per-thread instruction-based event queues.  Used for
145     * scheduling events based on number of instructions committed by
146     * a particular thread.
147     */
148    EventQueue **comInstEventQueue;
149
150    /**
151     * Vector of per-thread load-based event queues.  Used for
152     * scheduling events based on number of loads committed by
153     *a particular thread.
154     */
155    EventQueue **comLoadEventQueue;
156
157#if FULL_SYSTEM
158    System *system;
159
160    /**
161     * Serialize this object to the given output stream.
162     * @param os The stream to serialize to.
163     */
164    virtual void serialize(std::ostream &os);
165
166    /**
167     * Reconstruct the state of this object from a checkpoint.
168     * @param cp The checkpoint use.
169     * @param section The section name of this object
170     */
171    virtual void unserialize(Checkpoint *cp, const std::string &section);
172
173#endif
174
175    /**
176     * Return pointer to CPU's branch predictor (NULL if none).
177     * @return Branch predictor pointer.
178     */
179    virtual BranchPred *getBranchPred() { return NULL; };
180
181    virtual Counter totalInstructions() const { return 0; }
182
183    // Function tracing
184  private:
185    bool functionTracingEnabled;
186    std::ostream *functionTraceStream;
187    Addr currentFunctionStart;
188    Addr currentFunctionEnd;
189    Tick functionEntryTick;
190    void enableFunctionTrace();
191    void traceFunctionsInternal(Addr pc);
192
193  protected:
194    void traceFunctions(Addr pc)
195    {
196        if (functionTracingEnabled)
197            traceFunctionsInternal(pc);
198    }
199
200  private:
201    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
202
203  public:
204    static int numSimulatedCPUs() { return cpuList.size(); }
205    static Counter numSimulatedInstructions()
206    {
207        Counter total = 0;
208
209        int size = cpuList.size();
210        for (int i = 0; i < size; ++i)
211            total += cpuList[i]->totalInstructions();
212
213        return total;
214    }
215
216  public:
217    // Number of CPU cycles simulated
218    Stats::Scalar<> numCycles;
219};
220
221#endif // __CPU_BASE_HH__
222