base.hh revision 180 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __BASE_CPU_HH__
30#define __BASE_CPU_HH__
31
32#include <vector>
33
34#include "sim/eventq.hh"
35#include "sim/sim_object.hh"
36
37#include "targetarch/isa_traits.hh"	// for Addr
38
39#ifdef FULL_SYSTEM
40class System;
41#endif
42
43class BranchPred;
44class ExecContext;
45
46class BaseCPU : public SimObject
47{
48#ifdef FULL_SYSTEM
49  protected:
50    Tick frequency;
51    uint8_t interrupts[NumInterruptLevels];
52    uint64_t intstatus;
53
54  public:
55    virtual void post_interrupt(int int_num, int index);
56    virtual void clear_interrupt(int int_num, int index);
57    virtual void clear_interrupts();
58
59    bool check_interrupt(int int_num) const {
60        if (int_num > NumInterruptLevels)
61            panic("int_num out of bounds\n");
62
63        return interrupts[int_num] != 0;
64    }
65
66    bool check_interrupts() const { return intstatus != 0; }
67    uint64_t intr_status() const { return intstatus; }
68
69    Tick getFreq() const { return frequency; }
70#endif
71
72  protected:
73    std::vector<ExecContext *> execContexts;
74
75  public:
76    virtual void execCtxStatusChg() {}
77
78  public:
79
80#ifdef FULL_SYSTEM
81    BaseCPU(const std::string &_name, int _number_of_threads,
82            Counter max_insts_any_thread, Counter max_insts_all_threads,
83            Counter max_loads_any_thread, Counter max_loads_all_threads,
84            System *_system, Tick freq);
85#else
86    BaseCPU(const std::string &_name, int _number_of_threads,
87            Counter max_insts_any_thread = 0,
88            Counter max_insts_all_threads = 0,
89            Counter max_loads_any_thread = 0,
90            Counter max_loads_all_threads = 0);
91#endif
92
93    virtual ~BaseCPU() {}
94
95    virtual void regStats();
96
97    virtual void registerExecContexts();
98
99    /// Prepare for another CPU to take over execution.  Called by
100    /// takeOverFrom() on its argument.
101    virtual void switchOut();
102
103    /// Take over execution from the given CPU.  Used for warm-up and
104    /// sampling.
105    virtual void takeOverFrom(BaseCPU *);
106
107    /**
108     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
109     * This is a constant for the duration of the simulation.
110     */
111    int number_of_threads;
112
113    /**
114     * Vector of per-thread instruction-based event queues.  Used for
115     * scheduling events based on number of instructions committed by
116     * a particular thread.
117     */
118    EventQueue **comInsnEventQueue;
119
120    /**
121     * Vector of per-thread load-based event queues.  Used for
122     * scheduling events based on number of loads committed by
123     *a particular thread.
124     */
125    EventQueue **comLoadEventQueue;
126
127#ifdef FULL_SYSTEM
128    System *system;
129#endif
130
131    /**
132     * Return pointer to CPU's branch predictor (NULL if none).
133     * @return Branch predictor pointer.
134     */
135    virtual BranchPred *getBranchPred() { return NULL; };
136
137  private:
138    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
139
140  public:
141    static int numSimulatedCPUs() { return cpuList.size(); }
142};
143
144#endif // __BASE_CPU_HH__
145