base.hh revision 1634
1451SN/A/* 21762SN/A * Copyright (c) 2002-2004 The Regents of The University of Michigan 3451SN/A * All rights reserved. 4451SN/A * 5451SN/A * Redistribution and use in source and binary forms, with or without 6451SN/A * modification, are permitted provided that the following conditions are 7451SN/A * met: redistributions of source code must retain the above copyright 8451SN/A * notice, this list of conditions and the following disclaimer; 9451SN/A * redistributions in binary form must reproduce the above copyright 10451SN/A * notice, this list of conditions and the following disclaimer in the 11451SN/A * documentation and/or other materials provided with the distribution; 12451SN/A * neither the name of the copyright holders nor the names of its 13451SN/A * contributors may be used to endorse or promote products derived from 14451SN/A * this software without specific prior written permission. 15451SN/A * 16451SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17451SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18451SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19451SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20451SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21451SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22451SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23451SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24451SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25451SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26451SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 29451SN/A#ifndef __BASE_CPU_HH__ 30451SN/A#define __BASE_CPU_HH__ 31451SN/A 32451SN/A#include <vector> 332093SN/A 342093SN/A#include "base/statistics.hh" 352093SN/A#include "cpu/sampling_cpu/sampling_cpu.hh" 36451SN/A#include "sim/eventq.hh" 37451SN/A#include "sim/sim_object.hh" 38451SN/A#include "targetarch/isa_traits.hh" 392093SN/A 402093SN/A#ifdef FULL_SYSTEM 413113Sgblack@eecs.umich.educlass System; 422093SN/A#endif 433113Sgblack@eecs.umich.edu 442423SN/Aclass BranchPred; 452093SN/Aclass ExecContext; 462093SN/A 472093SN/Aclass BaseCPU : public SimObject 482093SN/A{ 492093SN/A protected: 503113Sgblack@eecs.umich.edu // CPU's clock period in terms of the number of ticks of curTime. 513113Sgblack@eecs.umich.edu Tick cycleTime; 522093SN/A 532093SN/A public: 542093SN/A inline Tick frequency() const { return Clock::Frequency / cycleTime; } 552093SN/A inline Tick cycles(int numCycles) const { return cycleTime * numCycles; } 562093SN/A inline Tick curCycle() const { return curTick / cycleTime; } 573122Sgblack@eecs.umich.edu 582093SN/A#ifdef FULL_SYSTEM 592093SN/A protected: 602093SN/A uint64_t interrupts[NumInterruptLevels]; 613122Sgblack@eecs.umich.edu uint64_t intstatus; 622093SN/A 632093SN/A public: 642093SN/A virtual void post_interrupt(int int_num, int index); 653113Sgblack@eecs.umich.edu virtual void clear_interrupt(int int_num, int index); 663113Sgblack@eecs.umich.edu virtual void clear_interrupts(); 673113Sgblack@eecs.umich.edu bool checkInterrupts; 682093SN/A 692093SN/A bool check_interrupt(int int_num) const { 702093SN/A if (int_num > NumInterruptLevels) 712093SN/A panic("int_num out of bounds\n"); 722093SN/A 732093SN/A return interrupts[int_num] != 0; 742093SN/A } 752093SN/A 762093SN/A bool check_interrupts() const { return intstatus != 0; } 772093SN/A uint64_t intr_status() const { return intstatus; } 782093SN/A#endif 792093SN/A 802093SN/A protected: 812093SN/A std::vector<ExecContext *> execContexts; 822093SN/A 832093SN/A public: 843113Sgblack@eecs.umich.edu 852093SN/A /// Notify the CPU that the indicated context is now active. The 862093SN/A /// delay parameter indicates the number of ticks to wait before 873113Sgblack@eecs.umich.edu /// executing (typically 0 or 1). 882093SN/A virtual void activateContext(int thread_num, int delay) {} 892093SN/A 902093SN/A /// Notify the CPU that the indicated context is now suspended. 912093SN/A virtual void suspendContext(int thread_num) {} 922093SN/A 932093SN/A /// Notify the CPU that the indicated context is now deallocated. 942093SN/A virtual void deallocateContext(int thread_num) {} 952093SN/A 962093SN/A /// Notify the CPU that the indicated context is now halted. 972093SN/A virtual void haltContext(int thread_num) {} 982093SN/A 992093SN/A public: 1002093SN/A struct Params 1013113Sgblack@eecs.umich.edu { 1022093SN/A std::string name; 1033113Sgblack@eecs.umich.edu int numberOfThreads; 1042093SN/A bool deferRegistration; 1053113Sgblack@eecs.umich.edu Counter max_insts_any_thread; 1062093SN/A Counter max_insts_all_threads; 1072093SN/A Counter max_loads_any_thread; 1083113Sgblack@eecs.umich.edu Counter max_loads_all_threads; 1092093SN/A Tick cycleTime; 1102093SN/A bool functionTrace; 1112093SN/A Tick functionTraceStart; 1122093SN/A#ifdef FULL_SYSTEM 1132093SN/A System *system; 1142093SN/A#endif 1152093SN/A }; 1162093SN/A 1172093SN/A const Params *params; 1182093SN/A 1192093SN/A BaseCPU(Params *params); 1202093SN/A virtual ~BaseCPU(); 1212093SN/A 1222093SN/A virtual void init(); 1232093SN/A virtual void regStats(); 1242093SN/A 1252093SN/A void registerExecContexts(); 1262093SN/A 1272093SN/A /// Prepare for another CPU to take over execution. When it is 1282093SN/A /// is ready (drained pipe) it signals the sampler. 1292093SN/A virtual void switchOut(SamplingCPU *); 1302093SN/A 1312093SN/A /// Take over execution from the given CPU. Used for warm-up and 1322093SN/A /// sampling. 1332093SN/A virtual void takeOverFrom(BaseCPU *); 1342093SN/A 1352093SN/A /** 1362093SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 1372093SN/A * This is a constant for the duration of the simulation. 1382093SN/A */ 1392093SN/A int number_of_threads; 1402093SN/A 1412093SN/A /** 1422093SN/A * Vector of per-thread instruction-based event queues. Used for 1432093SN/A * scheduling events based on number of instructions committed by 1442093SN/A * a particular thread. 1452093SN/A */ 1462093SN/A EventQueue **comInstEventQueue; 1472093SN/A 1482093SN/A /** 1492093SN/A * Vector of per-thread load-based event queues. Used for 1502093SN/A * scheduling events based on number of loads committed by 1512093SN/A *a particular thread. 1522093SN/A */ 1532093SN/A EventQueue **comLoadEventQueue; 1542093SN/A 1552093SN/A#ifdef FULL_SYSTEM 1562093SN/A System *system; 1572093SN/A 1582093SN/A /** 1592093SN/A * Serialize this object to the given output stream. 1602093SN/A * @param os The stream to serialize to. 1612093SN/A */ 1622093SN/A virtual void serialize(std::ostream &os); 1632093SN/A 1642093SN/A /** 1652093SN/A * Reconstruct the state of this object from a checkpoint. 166451SN/A * @param cp The checkpoint use. 167 * @param section The section name of this object 168 */ 169 virtual void unserialize(Checkpoint *cp, const std::string §ion); 170 171#endif 172 173 /** 174 * Return pointer to CPU's branch predictor (NULL if none). 175 * @return Branch predictor pointer. 176 */ 177 virtual BranchPred *getBranchPred() { return NULL; }; 178 179 virtual Counter totalInstructions() const { return 0; } 180 181 // Function tracing 182 private: 183 bool functionTracingEnabled; 184 std::ostream *functionTraceStream; 185 Addr currentFunctionStart; 186 Addr currentFunctionEnd; 187 Tick functionEntryTick; 188 void enableFunctionTrace(); 189 void traceFunctionsInternal(Addr pc); 190 191 protected: 192 void traceFunctions(Addr pc) 193 { 194 if (functionTracingEnabled) 195 traceFunctionsInternal(pc); 196 } 197 198 private: 199 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 200 201 public: 202 static int numSimulatedCPUs() { return cpuList.size(); } 203 static Counter numSimulatedInstructions() 204 { 205 Counter total = 0; 206 207 int size = cpuList.size(); 208 for (int i = 0; i < size; ++i) 209 total += cpuList[i]->totalInstructions(); 210 211 return total; 212 } 213 214 public: 215 // Number of CPU cycles simulated 216 Stats::Scalar<> numCycles; 217}; 218 219#endif // __BASE_CPU_HH__ 220