base.hh revision 14197
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2011-2013, 2017 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 519850Sandreas.hansson@arm.com// Before we do anything else, check if this build is the NULL ISA, 529850Sandreas.hansson@arm.com// and if so stop here 539850Sandreas.hansson@arm.com#include "config/the_isa.hh" 549850Sandreas.hansson@arm.com#if THE_ISA == NULL_ISA 559850Sandreas.hansson@arm.com#include "arch/null/cpu_dummy.hh" 569850Sandreas.hansson@arm.com#else 578745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 584182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 595664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 60707SN/A#include "base/statistics.hh" 6113892Sgabeblack@google.com#include "sim/clocked_object.hh" 6256SN/A#include "sim/eventq.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 644776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 6510464SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 6612284Sjose.marinho@arm.com#include "sim/probe/probe.hh" 679814Sandreas.hansson@arm.com#include "sim/system.hh" 6810529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 692SN/A 7010529Smorr@cs.wisc.educlass BaseCPU; 718901Sandreas.hansson@arm.comstruct BaseCPUParams; 722315SN/Aclass CheckerCPU; 732680Sktlim@umich.educlass ThreadContext; 742SN/A 7510529Smorr@cs.wisc.edustruct AddressMonitor 7610529Smorr@cs.wisc.edu{ 7710529Smorr@cs.wisc.edu AddressMonitor(); 7810529Smorr@cs.wisc.edu bool doMonitor(PacketPtr pkt); 7910529Smorr@cs.wisc.edu 8010529Smorr@cs.wisc.edu bool armed; 8110529Smorr@cs.wisc.edu Addr vAddr; 8210529Smorr@cs.wisc.edu Addr pAddr; 8310529Smorr@cs.wisc.edu uint64_t val; 8410529Smorr@cs.wisc.edu bool waiting; // 0=normal, 1=mwaiting 8510529Smorr@cs.wisc.edu bool gotWakeup; 8610529Smorr@cs.wisc.edu}; 8710529Smorr@cs.wisc.edu 882356SN/Aclass CPUProgressEvent : public Event 892356SN/A{ 902356SN/A protected: 916144Sksewell@umich.edu Tick _interval; 922356SN/A Counter lastNumInst; 932356SN/A BaseCPU *cpu; 946144Sksewell@umich.edu bool _repeatEvent; 952356SN/A 962356SN/A public: 976144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 982356SN/A 992356SN/A void process(); 1002356SN/A 1016144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 1026144Sksewell@umich.edu Tick interval() { return _interval; } 1036144Sksewell@umich.edu 1046144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 1056144Sksewell@umich.edu 1065336Shines@cs.fsu.edu virtual const char *description() const; 1072356SN/A}; 1082356SN/A 10913892Sgabeblack@google.comclass BaseCPU : public ClockedObject 1102SN/A{ 1111634SN/A protected: 1129157Sandreas.hansson@arm.com 11310662SAli.Saidi@ARM.com /// Instruction count used for SPARC misc register 11410662SAli.Saidi@ARM.com /// @todo unify this with the counters that cpus individually keep 1153814Ssaidi@eecs.umich.edu Tick instCnt; 11610662SAli.Saidi@ARM.com 1175712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1185712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1195715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1205712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1215712Shsul@eecs.umich.edu int _cpuId; 1221634SN/A 12310190Sakash.bagdia@arm.com /** Each cpu will have a socket ID that corresponds to its physical location 12410190Sakash.bagdia@arm.com * in the system. This is usually used to bucket cpu cores under single DVFS 12510190Sakash.bagdia@arm.com * domain. This information may also be required by the OS to identify the 12610190Sakash.bagdia@arm.com * cpu core grouping (as in the case of ARM via MPIDR register) 12710190Sakash.bagdia@arm.com */ 12810190Sakash.bagdia@arm.com const uint32_t _socketId; 12910190Sakash.bagdia@arm.com 1308832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1318832SAli.Saidi@ARM.com MasterID _instMasterId; 1328832SAli.Saidi@ARM.com 1338832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1348832SAli.Saidi@ARM.com MasterID _dataMasterId; 1358832SAli.Saidi@ARM.com 1369332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1379332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1389332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1399332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1409332Sdam.sunwoo@arm.com */ 1419332Sdam.sunwoo@arm.com uint32_t _taskId; 1429332Sdam.sunwoo@arm.com 1439332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1449332Sdam.sunwoo@arm.com * used to generate a taskId */ 1459332Sdam.sunwoo@arm.com uint32_t _pid; 1469332Sdam.sunwoo@arm.com 1479430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1489430SAndreas.Sandberg@ARM.com bool _switchedOut; 1499430SAndreas.Sandberg@ARM.com 1509814Sandreas.hansson@arm.com /** Cache the cache line size that we get from the system */ 1519814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 1529814Sandreas.hansson@arm.com 1531634SN/A public: 1548850Sandreas.hansson@arm.com 1558850Sandreas.hansson@arm.com /** 1568850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1578850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1588850Sandreas.hansson@arm.com * 1598850Sandreas.hansson@arm.com * @return a reference to the data port 1608850Sandreas.hansson@arm.com */ 1619608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1628850Sandreas.hansson@arm.com 1638850Sandreas.hansson@arm.com /** 16414197Sgabeblack@google.com * Returns a sendFunctional delegate for use with port proxies. 16514197Sgabeblack@google.com */ 16614197Sgabeblack@google.com virtual PortProxy::SendFunctionalFunc 16714197Sgabeblack@google.com getSendFunctional() 16814197Sgabeblack@google.com { 16914197Sgabeblack@google.com MasterPort &port = getDataPort(); 17014197Sgabeblack@google.com return [&port](PacketPtr pkt)->void { port.sendFunctional(pkt); }; 17114197Sgabeblack@google.com } 17214197Sgabeblack@google.com 17314197Sgabeblack@google.com /** 1748850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1758850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1768850Sandreas.hansson@arm.com * 1778850Sandreas.hansson@arm.com * @return a reference to the instruction port 1788850Sandreas.hansson@arm.com */ 1799608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1808850Sandreas.hansson@arm.com 1815712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 18210110Sandreas.hansson@arm.com int cpuId() const { return _cpuId; } 1835712Shsul@eecs.umich.edu 18410190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 18510190Sakash.bagdia@arm.com uint32_t socketId() const { return _socketId; } 18610190Sakash.bagdia@arm.com 1878832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 18813954Sgiacomo.gabrielli@arm.com MasterID dataMasterId() const { return _dataMasterId; } 1898832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 19013954Sgiacomo.gabrielli@arm.com MasterID instMasterId() const { return _instMasterId; } 1918832SAli.Saidi@ARM.com 1928850Sandreas.hansson@arm.com /** 19313784Sgabeblack@google.com * Get a port on this CPU. All CPUs have a data and 1948926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1958926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1968850Sandreas.hansson@arm.com * 1978850Sandreas.hansson@arm.com * @param if_name the port name 1988850Sandreas.hansson@arm.com * @param idx ignored index 1998850Sandreas.hansson@arm.com * 2008922Swilliam.wang@arm.com * @return a reference to the port with the given name 2018850Sandreas.hansson@arm.com */ 20213784Sgabeblack@google.com Port &getPort(const std::string &if_name, 20313784Sgabeblack@google.com PortID idx=InvalidPortID) override; 2048850Sandreas.hansson@arm.com 2059332Sdam.sunwoo@arm.com /** Get cpu task id */ 2069332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 2079332Sdam.sunwoo@arm.com /** Set cpu task id */ 2089332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 2099332Sdam.sunwoo@arm.com 2109332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 2119332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 2129332Sdam.sunwoo@arm.com 2137914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 2147914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 2153814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 2163814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 2171634SN/A 2185664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2195664Sgblack@eecs.umich.edu 2202SN/A protected: 22111150Smitch.hayenga@arm.com std::vector<TheISA::Interrupts*> interrupts; 2222SN/A 2232SN/A public: 2245645Sgblack@eecs.umich.edu TheISA::Interrupts * 22511150Smitch.hayenga@arm.com getInterruptController(ThreadID tid) 2265645Sgblack@eecs.umich.edu { 22711150Smitch.hayenga@arm.com if (interrupts.empty()) 22811150Smitch.hayenga@arm.com return NULL; 22911150Smitch.hayenga@arm.com 23011150Smitch.hayenga@arm.com assert(interrupts.size() > tid); 23111150Smitch.hayenga@arm.com return interrupts[tid]; 2325645Sgblack@eecs.umich.edu } 2335645Sgblack@eecs.umich.edu 23411151Smitch.hayenga@arm.com virtual void wakeup(ThreadID tid) = 0; 2355807Snate@binkert.org 2365807Snate@binkert.org void 23711150Smitch.hayenga@arm.com postInterrupt(ThreadID tid, int int_num, int index) 2385807Snate@binkert.org { 23911150Smitch.hayenga@arm.com interrupts[tid]->post(int_num, index); 2408779Sgblack@eecs.umich.edu if (FullSystem) 24111151Smitch.hayenga@arm.com wakeup(tid); 2425807Snate@binkert.org } 2435807Snate@binkert.org 2445807Snate@binkert.org void 24511150Smitch.hayenga@arm.com clearInterrupt(ThreadID tid, int int_num, int index) 2465807Snate@binkert.org { 24711150Smitch.hayenga@arm.com interrupts[tid]->clear(int_num, index); 2485807Snate@binkert.org } 2495807Snate@binkert.org 2505807Snate@binkert.org void 25111150Smitch.hayenga@arm.com clearInterrupts(ThreadID tid) 2525807Snate@binkert.org { 25311150Smitch.hayenga@arm.com interrupts[tid]->clearAll(); 2545807Snate@binkert.org } 2552SN/A 2565704Snate@binkert.org bool 2575704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2585704Snate@binkert.org { 25911150Smitch.hayenga@arm.com return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc); 2605704Snate@binkert.org } 2611917SN/A 26212127Sspwilson2@wisc.edu void processProfileEvent(); 26312127Sspwilson2@wisc.edu EventFunctionWrapper * profileEvent; 2642SN/A 2652SN/A protected: 2662680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2672SN/A 2684776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2694776Sgblack@eecs.umich.edu 2702SN/A public: 271393SN/A 27211050Sandreas.hansson@arm.com 27311050Sandreas.hansson@arm.com /** Invalid or unknown Pid. Possible when operating system is not present 27411050Sandreas.hansson@arm.com * or has not assigned a pid yet */ 27511050Sandreas.hansson@arm.com static const uint32_t invldPid = std::numeric_limits<uint32_t>::max(); 27611050Sandreas.hansson@arm.com 2777764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2787764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2797764Sgblack@eecs.umich.edu 2804776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2814776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2824776Sgblack@eecs.umich.edu 28310407Smitch.hayenga@arm.com /// Notify the CPU that the indicated context is now active. 28411526Sdavid.guillen@arm.com virtual void activateContext(ThreadID thread_num); 285393SN/A 286393SN/A /// Notify the CPU that the indicated context is now suspended. 28711526Sdavid.guillen@arm.com /// Check if possible to enter a lower power state 28811526Sdavid.guillen@arm.com virtual void suspendContext(ThreadID thread_num); 289393SN/A 290393SN/A /// Notify the CPU that the indicated context is now halted. 29112284Sjose.marinho@arm.com virtual void haltContext(ThreadID thread_num); 2922SN/A 2934000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2944000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2954000Ssaidi@eecs.umich.edu 2964000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2979652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2984000Ssaidi@eecs.umich.edu 29910030SAli.Saidi@ARM.com /// Get the number of thread contexts available 30014016SAndrea.Mondelli@ucf.edu unsigned numContexts() { 30114016SAndrea.Mondelli@ucf.edu return static_cast<unsigned>(threadContexts.size()); 30214016SAndrea.Mondelli@ucf.edu } 30310030SAli.Saidi@ARM.com 30411435Smitch.hayenga@arm.com /// Convert ContextID to threadID 30511435Smitch.hayenga@arm.com ThreadID contextToThread(ContextID cid) 30611435Smitch.hayenga@arm.com { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); } 30711435Smitch.hayenga@arm.com 3082SN/A public: 3095529Snate@binkert.org typedef BaseCPUParams Params; 3105529Snate@binkert.org const Params *params() const 3115529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 3128876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 3131191SN/A virtual ~BaseCPU(); 3142SN/A 31511169Sandreas.hansson@arm.com void init() override; 31611169Sandreas.hansson@arm.com void startup() override; 31711169Sandreas.hansson@arm.com void regStats() override; 3182SN/A 31911168Sandreas.hansson@arm.com void regProbePoints() override; 32010464SAndreas.Sandberg@ARM.com 3212680Sktlim@umich.edu void registerThreadContexts(); 322180SN/A 32312276Sanouk.vanlaer@arm.com // Functions to deschedule and reschedule the events to enter the 32412276Sanouk.vanlaer@arm.com // power gating sleep before and after checkpoiting respectively. 32512276Sanouk.vanlaer@arm.com void deschedulePowerGatingEvent(); 32612276Sanouk.vanlaer@arm.com void schedulePowerGatingEvent(); 32712276Sanouk.vanlaer@arm.com 3289254SAndreas.Sandberg@arm.com /** 3299254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 3309254SAndreas.Sandberg@arm.com * 3319254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 3329254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 3339254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 3349254SAndreas.Sandberg@arm.com */ 3352798Sktlim@umich.edu virtual void switchOut(); 336180SN/A 3379254SAndreas.Sandberg@arm.com /** 3389254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 3399254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3409254SAndreas.Sandberg@arm.com * 3419254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3429254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3439254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3449254SAndreas.Sandberg@arm.com * CPU. 3459254SAndreas.Sandberg@arm.com * 3469254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3479254SAndreas.Sandberg@arm.com */ 3489254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 349180SN/A 350124SN/A /** 3519446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3529446SAndreas.Sandberg@ARM.com * 3539446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3549446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3559446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3569446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3579446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3589446SAndreas.Sandberg@ARM.com */ 3599446SAndreas.Sandberg@ARM.com void flushTLBs(); 3609446SAndreas.Sandberg@ARM.com 3619446SAndreas.Sandberg@ARM.com /** 3629430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3639430SAndreas.Sandberg@ARM.com * 3649430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3659430SAndreas.Sandberg@ARM.com */ 3669430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3679430SAndreas.Sandberg@ARM.com 3689430SAndreas.Sandberg@ARM.com /** 3699523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3709523SAndreas.Sandberg@ARM.com * CPU. 3719523SAndreas.Sandberg@ARM.com * 3729523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3739523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3749523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3759523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3769523SAndreas.Sandberg@ARM.com */ 3779523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3789523SAndreas.Sandberg@ARM.com 3799523SAndreas.Sandberg@ARM.com /** 380124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 381124SN/A * This is a constant for the duration of the simulation. 382124SN/A */ 3836221Snate@binkert.org ThreadID numThreads; 3842SN/A 385124SN/A /** 386124SN/A * Vector of per-thread instruction-based event queues. Used for 387124SN/A * scheduling events based on number of instructions committed by 388124SN/A * a particular thread. 389124SN/A */ 390503SN/A EventQueue **comInstEventQueue; 3912SN/A 392124SN/A /** 393124SN/A * Vector of per-thread load-based event queues. Used for 394124SN/A * scheduling events based on number of loads committed by 395124SN/A *a particular thread. 396124SN/A */ 397124SN/A EventQueue **comLoadEventQueue; 398124SN/A 3992SN/A System *system; 400921SN/A 401921SN/A /** 4029814Sandreas.hansson@arm.com * Get the cache line size of the system. 4039814Sandreas.hansson@arm.com */ 4049814Sandreas.hansson@arm.com inline unsigned int cacheLineSize() const { return _cacheLineSize; } 4059814Sandreas.hansson@arm.com 4069814Sandreas.hansson@arm.com /** 407921SN/A * Serialize this object to the given output stream. 4089448SAndreas.Sandberg@ARM.com * 4099448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 4109448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 4119448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 4129448SAndreas.Sandberg@ARM.com * reuse. 4139448SAndreas.Sandberg@ARM.com * 41414016SAndrea.Mondelli@ucf.edu * @param cp The stream to serialize to. 415921SN/A */ 41611168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 417921SN/A 418921SN/A /** 419921SN/A * Reconstruct the state of this object from a checkpoint. 4209448SAndreas.Sandberg@ARM.com * 4219448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 4229448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 4239448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 4249448SAndreas.Sandberg@ARM.com * promotes better code reuse. 4259448SAndreas.Sandberg@ARM.com 426921SN/A * @param cp The checkpoint use. 427921SN/A */ 42811168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 429921SN/A 430124SN/A /** 4319448SAndreas.Sandberg@ARM.com * Serialize a single thread. 4329448SAndreas.Sandberg@ARM.com * 43314016SAndrea.Mondelli@ucf.edu * @param cp The stream to serialize to. 4349448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4359448SAndreas.Sandberg@ARM.com */ 43610905Sandreas.sandberg@arm.com virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {}; 4379448SAndreas.Sandberg@ARM.com 4389448SAndreas.Sandberg@ARM.com /** 4399448SAndreas.Sandberg@ARM.com * Unserialize one thread. 4409448SAndreas.Sandberg@ARM.com * 4419448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 4429448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4439448SAndreas.Sandberg@ARM.com */ 44410905Sandreas.sandberg@arm.com virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {}; 4459448SAndreas.Sandberg@ARM.com 4468834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 4478834Satgutier@umich.edu 4488834Satgutier@umich.edu virtual Counter totalOps() const = 0; 449707SN/A 4509749Sandreas@sandberg.pp.se /** 4519749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4529749Sandreas@sandberg.pp.se * predefined number of instructions. 4539749Sandreas@sandberg.pp.se * 4549749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4559749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4569749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4579749Sandreas@sandberg.pp.se * instructions rather than ticks. 4589749Sandreas@sandberg.pp.se * 4599749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4609749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4619749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4629749Sandreas@sandberg.pp.se */ 4639749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4649749Sandreas@sandberg.pp.se 4659749Sandreas@sandberg.pp.se /** 4669749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4679749Sandreas@sandberg.pp.se * predefined number of load operations. 4689749Sandreas@sandberg.pp.se * 4699749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4709749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4719749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4729749Sandreas@sandberg.pp.se * loads rather than ticks. 4739749Sandreas@sandberg.pp.se * 4749749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4759749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4769749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4779749Sandreas@sandberg.pp.se */ 4789749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4799749Sandreas@sandberg.pp.se 48011415SGeoffrey.Blake@arm.com /** 48111415SGeoffrey.Blake@arm.com * Get the number of instructions executed by the specified thread 48211415SGeoffrey.Blake@arm.com * on this CPU. Used by Python to control simulation. 48311415SGeoffrey.Blake@arm.com * 48411415SGeoffrey.Blake@arm.com * @param tid Thread monitor 48511415SGeoffrey.Blake@arm.com * @return Number of instructions executed 48611415SGeoffrey.Blake@arm.com */ 48711415SGeoffrey.Blake@arm.com uint64_t getCurrentInstCount(ThreadID tid); 48811415SGeoffrey.Blake@arm.com 48910464SAndreas.Sandberg@ARM.com public: 49010464SAndreas.Sandberg@ARM.com /** 49110464SAndreas.Sandberg@ARM.com * @{ 49210464SAndreas.Sandberg@ARM.com * @name PMU Probe points. 49310464SAndreas.Sandberg@ARM.com */ 49410464SAndreas.Sandberg@ARM.com 49510464SAndreas.Sandberg@ARM.com /** 49610464SAndreas.Sandberg@ARM.com * Helper method to trigger PMU probes for a committed 49710464SAndreas.Sandberg@ARM.com * instruction. 49810464SAndreas.Sandberg@ARM.com * 49910464SAndreas.Sandberg@ARM.com * @param inst Instruction that just committed 50013818Sjavier.bueno@metempsy.com * @param pc PC of the instruction that just committed 50110464SAndreas.Sandberg@ARM.com */ 50213818Sjavier.bueno@metempsy.com virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc); 50310464SAndreas.Sandberg@ARM.com 50412284Sjose.marinho@arm.com protected: 50510464SAndreas.Sandberg@ARM.com /** 50610464SAndreas.Sandberg@ARM.com * Helper method to instantiate probe points belonging to this 50710464SAndreas.Sandberg@ARM.com * object. 50810464SAndreas.Sandberg@ARM.com * 50910464SAndreas.Sandberg@ARM.com * @param name Name of the probe point. 51010464SAndreas.Sandberg@ARM.com * @return A unique_ptr to the new probe point. 51110464SAndreas.Sandberg@ARM.com */ 51210464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr pmuProbePoint(const char *name); 51310464SAndreas.Sandberg@ARM.com 51410464SAndreas.Sandberg@ARM.com /** 51510464SAndreas.Sandberg@ARM.com * Instruction commit probe point. 51610464SAndreas.Sandberg@ARM.com * 51710464SAndreas.Sandberg@ARM.com * This probe point is triggered whenever one or more instructions 51810464SAndreas.Sandberg@ARM.com * are committed. It is normally triggered once for every 51910464SAndreas.Sandberg@ARM.com * instruction. However, CPU models committing bundles of 52010464SAndreas.Sandberg@ARM.com * instructions may call notify once for the entire bundle. 52110464SAndreas.Sandberg@ARM.com */ 52210464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredInsts; 52313818Sjavier.bueno@metempsy.com ProbePoints::PMUUPtr ppRetiredInstsPC; 52410464SAndreas.Sandberg@ARM.com 52510464SAndreas.Sandberg@ARM.com /** Retired load instructions */ 52610464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredLoads; 52710464SAndreas.Sandberg@ARM.com /** Retired store instructions */ 52810464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredStores; 52910464SAndreas.Sandberg@ARM.com 53010464SAndreas.Sandberg@ARM.com /** Retired branches (any type) */ 53110464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredBranches; 53210464SAndreas.Sandberg@ARM.com 53312284Sjose.marinho@arm.com /** CPU cycle counter even if any thread Context is suspended*/ 53412284Sjose.marinho@arm.com ProbePoints::PMUUPtr ppAllCycles; 53512284Sjose.marinho@arm.com 53612284Sjose.marinho@arm.com /** CPU cycle counter, only counts if any thread contexts is active **/ 53712284Sjose.marinho@arm.com ProbePoints::PMUUPtr ppActiveCycles; 53812284Sjose.marinho@arm.com 53912284Sjose.marinho@arm.com /** 54012284Sjose.marinho@arm.com * ProbePoint that signals transitions of threadContexts sets. 54112284Sjose.marinho@arm.com * The ProbePoint reports information through it bool parameter. 54212284Sjose.marinho@arm.com * - If the parameter is true then the last enabled threadContext of the 54312284Sjose.marinho@arm.com * CPU object was disabled. 54412284Sjose.marinho@arm.com * - If the parameter is false then a threadContext was enabled, all the 54512284Sjose.marinho@arm.com * remaining threadContexts are disabled. 54612284Sjose.marinho@arm.com */ 54712284Sjose.marinho@arm.com ProbePointArg<bool> *ppSleeping; 54810464SAndreas.Sandberg@ARM.com /** @} */ 54910464SAndreas.Sandberg@ARM.com 55012284Sjose.marinho@arm.com enum CPUState { 55112284Sjose.marinho@arm.com CPU_STATE_ON, 55212284Sjose.marinho@arm.com CPU_STATE_SLEEP, 55312284Sjose.marinho@arm.com CPU_STATE_WAKEUP 55412284Sjose.marinho@arm.com }; 55510464SAndreas.Sandberg@ARM.com 55612284Sjose.marinho@arm.com Cycles previousCycle; 55712284Sjose.marinho@arm.com CPUState previousState; 55812284Sjose.marinho@arm.com 55912284Sjose.marinho@arm.com /** base method keeping track of cycle progression **/ 56012284Sjose.marinho@arm.com inline void updateCycleCounters(CPUState state) 56112284Sjose.marinho@arm.com { 56212284Sjose.marinho@arm.com uint32_t delta = curCycle() - previousCycle; 56312284Sjose.marinho@arm.com 56412284Sjose.marinho@arm.com if (previousState == CPU_STATE_ON) { 56512284Sjose.marinho@arm.com ppActiveCycles->notify(delta); 56612284Sjose.marinho@arm.com } 56712284Sjose.marinho@arm.com 56812284Sjose.marinho@arm.com switch (state) 56912284Sjose.marinho@arm.com { 57012284Sjose.marinho@arm.com case CPU_STATE_WAKEUP: 57112284Sjose.marinho@arm.com ppSleeping->notify(false); 57212284Sjose.marinho@arm.com break; 57312284Sjose.marinho@arm.com case CPU_STATE_SLEEP: 57412284Sjose.marinho@arm.com ppSleeping->notify(true); 57512284Sjose.marinho@arm.com break; 57612284Sjose.marinho@arm.com default: 57712284Sjose.marinho@arm.com break; 57812284Sjose.marinho@arm.com } 57912284Sjose.marinho@arm.com 58012284Sjose.marinho@arm.com ppAllCycles->notify(delta); 58112284Sjose.marinho@arm.com 58212284Sjose.marinho@arm.com previousCycle = curCycle(); 58312284Sjose.marinho@arm.com previousState = state; 58412284Sjose.marinho@arm.com } 58510464SAndreas.Sandberg@ARM.com 5861191SN/A // Function tracing 5871191SN/A private: 5881191SN/A bool functionTracingEnabled; 5891191SN/A std::ostream *functionTraceStream; 5901191SN/A Addr currentFunctionStart; 5911191SN/A Addr currentFunctionEnd; 5921191SN/A Tick functionEntryTick; 5931191SN/A void enableFunctionTrace(); 5941191SN/A void traceFunctionsInternal(Addr pc); 5951191SN/A 5968662SAli.Saidi@ARM.com private: 5978662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 5988662SAli.Saidi@ARM.com 5998662SAli.Saidi@ARM.com public: 6001191SN/A void traceFunctions(Addr pc) 6011191SN/A { 6021191SN/A if (functionTracingEnabled) 6031191SN/A traceFunctionsInternal(pc); 6041191SN/A } 6051191SN/A 6062SN/A static int numSimulatedCPUs() { return cpuList.size(); } 6078834Satgutier@umich.edu static Counter numSimulatedInsts() 608707SN/A { 609707SN/A Counter total = 0; 610707SN/A 611707SN/A int size = cpuList.size(); 612707SN/A for (int i = 0; i < size; ++i) 6138834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 6148834Satgutier@umich.edu 6158834Satgutier@umich.edu return total; 6168834Satgutier@umich.edu } 6178834Satgutier@umich.edu 6188834Satgutier@umich.edu static Counter numSimulatedOps() 6198834Satgutier@umich.edu { 6208834Satgutier@umich.edu Counter total = 0; 6218834Satgutier@umich.edu 6228834Satgutier@umich.edu int size = cpuList.size(); 6238834Satgutier@umich.edu for (int i = 0; i < size; ++i) 6248834Satgutier@umich.edu total += cpuList[i]->totalOps(); 625707SN/A 626707SN/A return total; 627707SN/A } 628707SN/A 629707SN/A public: 630707SN/A // Number of CPU cycles simulated 6315999Snate@binkert.org Stats::Scalar numCycles; 6327914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 6337914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 63410529Smorr@cs.wisc.edu 63510529Smorr@cs.wisc.edu private: 63611148Smitch.hayenga@arm.com std::vector<AddressMonitor> addressMonitor; 63710529Smorr@cs.wisc.edu 63810529Smorr@cs.wisc.edu public: 63911148Smitch.hayenga@arm.com void armMonitor(ThreadID tid, Addr address); 64011148Smitch.hayenga@arm.com bool mwait(ThreadID tid, PacketPtr pkt); 64112406Sgabeblack@google.com void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb); 64211148Smitch.hayenga@arm.com AddressMonitor *getCpuAddrMonitor(ThreadID tid) 64311148Smitch.hayenga@arm.com { 64411148Smitch.hayenga@arm.com assert(tid < numThreads); 64511148Smitch.hayenga@arm.com return &addressMonitor[tid]; 64611148Smitch.hayenga@arm.com } 64711877Sbrandon.potter@amd.com 64812122Sjose.marinho@arm.com bool waitForRemoteGDB() const; 64912122Sjose.marinho@arm.com 65011877Sbrandon.potter@amd.com Cycles syscallRetryLatency; 65112277Sjose.marinho@arm.com 65212276Sanouk.vanlaer@arm.com // Enables CPU to enter power gating on a configurable cycle count 65312276Sanouk.vanlaer@arm.com protected: 65412277Sjose.marinho@arm.com void enterPwrGating(); 65512277Sjose.marinho@arm.com 65612276Sanouk.vanlaer@arm.com const Cycles pwrGatingLatency; 65712277Sjose.marinho@arm.com const bool powerGatingOnIdle; 65812276Sanouk.vanlaer@arm.com EventFunctionWrapper enterPwrGatingEvent; 6592SN/A}; 6602SN/A 6619850Sandreas.hansson@arm.com#endif // THE_ISA == NULL_ISA 6629850Sandreas.hansson@arm.com 6631717SN/A#endif // __CPU_BASE_HH__ 664