base.hh revision 13667
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2011-2013, 2017 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 519850Sandreas.hansson@arm.com// Before we do anything else, check if this build is the NULL ISA, 529850Sandreas.hansson@arm.com// and if so stop here 539850Sandreas.hansson@arm.com#include "config/the_isa.hh" 549850Sandreas.hansson@arm.com#if THE_ISA == NULL_ISA 559850Sandreas.hansson@arm.com#include "arch/null/cpu_dummy.hh" 569850Sandreas.hansson@arm.com#else 578745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 584182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 595664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 60707SN/A#include "base/statistics.hh" 618229Snate@binkert.org#include "mem/mem_object.hh" 6256SN/A#include "sim/eventq.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 644776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 6510464SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 6612284Sjose.marinho@arm.com#include "sim/probe/probe.hh" 679814Sandreas.hansson@arm.com#include "sim/system.hh" 6810529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 692SN/A 7010529Smorr@cs.wisc.educlass BaseCPU; 718901Sandreas.hansson@arm.comstruct BaseCPUParams; 722315SN/Aclass CheckerCPU; 732680Sktlim@umich.educlass ThreadContext; 742SN/A 7510529Smorr@cs.wisc.edustruct AddressMonitor 7610529Smorr@cs.wisc.edu{ 7710529Smorr@cs.wisc.edu AddressMonitor(); 7810529Smorr@cs.wisc.edu bool doMonitor(PacketPtr pkt); 7910529Smorr@cs.wisc.edu 8010529Smorr@cs.wisc.edu bool armed; 8110529Smorr@cs.wisc.edu Addr vAddr; 8210529Smorr@cs.wisc.edu Addr pAddr; 8310529Smorr@cs.wisc.edu uint64_t val; 8410529Smorr@cs.wisc.edu bool waiting; // 0=normal, 1=mwaiting 8510529Smorr@cs.wisc.edu bool gotWakeup; 8610529Smorr@cs.wisc.edu}; 8710529Smorr@cs.wisc.edu 882356SN/Aclass CPUProgressEvent : public Event 892356SN/A{ 902356SN/A protected: 916144Sksewell@umich.edu Tick _interval; 922356SN/A Counter lastNumInst; 932356SN/A BaseCPU *cpu; 946144Sksewell@umich.edu bool _repeatEvent; 952356SN/A 962356SN/A public: 976144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 982356SN/A 992356SN/A void process(); 1002356SN/A 1016144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 1026144Sksewell@umich.edu Tick interval() { return _interval; } 1036144Sksewell@umich.edu 1046144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 1056144Sksewell@umich.edu 1065336Shines@cs.fsu.edu virtual const char *description() const; 1072356SN/A}; 1082356SN/A 1092856Srdreslin@umich.educlass BaseCPU : public MemObject 1102SN/A{ 1111634SN/A protected: 1129157Sandreas.hansson@arm.com 11310662SAli.Saidi@ARM.com /// Instruction count used for SPARC misc register 11410662SAli.Saidi@ARM.com /// @todo unify this with the counters that cpus individually keep 1153814Ssaidi@eecs.umich.edu Tick instCnt; 11610662SAli.Saidi@ARM.com 1175712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1185712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1195715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1205712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1215712Shsul@eecs.umich.edu int _cpuId; 1221634SN/A 12310190Sakash.bagdia@arm.com /** Each cpu will have a socket ID that corresponds to its physical location 12410190Sakash.bagdia@arm.com * in the system. This is usually used to bucket cpu cores under single DVFS 12510190Sakash.bagdia@arm.com * domain. This information may also be required by the OS to identify the 12610190Sakash.bagdia@arm.com * cpu core grouping (as in the case of ARM via MPIDR register) 12710190Sakash.bagdia@arm.com */ 12810190Sakash.bagdia@arm.com const uint32_t _socketId; 12910190Sakash.bagdia@arm.com 1308832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1318832SAli.Saidi@ARM.com MasterID _instMasterId; 1328832SAli.Saidi@ARM.com 1338832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1348832SAli.Saidi@ARM.com MasterID _dataMasterId; 1358832SAli.Saidi@ARM.com 1369332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1379332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1389332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1399332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1409332Sdam.sunwoo@arm.com */ 1419332Sdam.sunwoo@arm.com uint32_t _taskId; 1429332Sdam.sunwoo@arm.com 1439332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1449332Sdam.sunwoo@arm.com * used to generate a taskId */ 1459332Sdam.sunwoo@arm.com uint32_t _pid; 1469332Sdam.sunwoo@arm.com 1479430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1489430SAndreas.Sandberg@ARM.com bool _switchedOut; 1499430SAndreas.Sandberg@ARM.com 1509814Sandreas.hansson@arm.com /** Cache the cache line size that we get from the system */ 1519814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 1529814Sandreas.hansson@arm.com 1531634SN/A public: 1548850Sandreas.hansson@arm.com 1558850Sandreas.hansson@arm.com /** 1568850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1578850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1588850Sandreas.hansson@arm.com * 1598850Sandreas.hansson@arm.com * @return a reference to the data port 1608850Sandreas.hansson@arm.com */ 1619608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1628850Sandreas.hansson@arm.com 1638850Sandreas.hansson@arm.com /** 1648850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1658850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1668850Sandreas.hansson@arm.com * 1678850Sandreas.hansson@arm.com * @return a reference to the instruction port 1688850Sandreas.hansson@arm.com */ 1699608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1708850Sandreas.hansson@arm.com 1715712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 17210110Sandreas.hansson@arm.com int cpuId() const { return _cpuId; } 1735712Shsul@eecs.umich.edu 17410190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 17510190Sakash.bagdia@arm.com uint32_t socketId() const { return _socketId; } 17610190Sakash.bagdia@arm.com 1778832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1788832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1798832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1808832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1818832SAli.Saidi@ARM.com 1828850Sandreas.hansson@arm.com /** 1838926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1848926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1858926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1868850Sandreas.hansson@arm.com * 1878850Sandreas.hansson@arm.com * @param if_name the port name 1888850Sandreas.hansson@arm.com * @param idx ignored index 1898850Sandreas.hansson@arm.com * 1908922Swilliam.wang@arm.com * @return a reference to the port with the given name 1918850Sandreas.hansson@arm.com */ 1929294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 19311169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 1948850Sandreas.hansson@arm.com 1959332Sdam.sunwoo@arm.com /** Get cpu task id */ 1969332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1979332Sdam.sunwoo@arm.com /** Set cpu task id */ 1989332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1999332Sdam.sunwoo@arm.com 2009332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 2019332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 2029332Sdam.sunwoo@arm.com 2037914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 2047914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 2053814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 2063814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 2071634SN/A 2085664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2095664Sgblack@eecs.umich.edu 2102SN/A protected: 21111150Smitch.hayenga@arm.com std::vector<TheISA::Interrupts*> interrupts; 2122SN/A 2132SN/A public: 2145645Sgblack@eecs.umich.edu TheISA::Interrupts * 21511150Smitch.hayenga@arm.com getInterruptController(ThreadID tid) 2165645Sgblack@eecs.umich.edu { 21711150Smitch.hayenga@arm.com if (interrupts.empty()) 21811150Smitch.hayenga@arm.com return NULL; 21911150Smitch.hayenga@arm.com 22011150Smitch.hayenga@arm.com assert(interrupts.size() > tid); 22111150Smitch.hayenga@arm.com return interrupts[tid]; 2225645Sgblack@eecs.umich.edu } 2235645Sgblack@eecs.umich.edu 22411151Smitch.hayenga@arm.com virtual void wakeup(ThreadID tid) = 0; 2255807Snate@binkert.org 2265807Snate@binkert.org void 22711150Smitch.hayenga@arm.com postInterrupt(ThreadID tid, int int_num, int index) 2285807Snate@binkert.org { 22911150Smitch.hayenga@arm.com interrupts[tid]->post(int_num, index); 2308779Sgblack@eecs.umich.edu if (FullSystem) 23111151Smitch.hayenga@arm.com wakeup(tid); 2325807Snate@binkert.org } 2335807Snate@binkert.org 2345807Snate@binkert.org void 23511150Smitch.hayenga@arm.com clearInterrupt(ThreadID tid, int int_num, int index) 2365807Snate@binkert.org { 23711150Smitch.hayenga@arm.com interrupts[tid]->clear(int_num, index); 2385807Snate@binkert.org } 2395807Snate@binkert.org 2405807Snate@binkert.org void 24111150Smitch.hayenga@arm.com clearInterrupts(ThreadID tid) 2425807Snate@binkert.org { 24311150Smitch.hayenga@arm.com interrupts[tid]->clearAll(); 2445807Snate@binkert.org } 2452SN/A 2465704Snate@binkert.org bool 2475704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2485704Snate@binkert.org { 24911150Smitch.hayenga@arm.com return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc); 2505704Snate@binkert.org } 2511917SN/A 25212127Sspwilson2@wisc.edu void processProfileEvent(); 25312127Sspwilson2@wisc.edu EventFunctionWrapper * profileEvent; 2542SN/A 2552SN/A protected: 2562680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2572SN/A 2584776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2594776Sgblack@eecs.umich.edu 2602SN/A public: 261393SN/A 26211050Sandreas.hansson@arm.com 26311050Sandreas.hansson@arm.com /** Invalid or unknown Pid. Possible when operating system is not present 26411050Sandreas.hansson@arm.com * or has not assigned a pid yet */ 26511050Sandreas.hansson@arm.com static const uint32_t invldPid = std::numeric_limits<uint32_t>::max(); 26611050Sandreas.hansson@arm.com 2677764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2687764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2697764Sgblack@eecs.umich.edu 2704776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2714776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2724776Sgblack@eecs.umich.edu 27310407Smitch.hayenga@arm.com /// Notify the CPU that the indicated context is now active. 27411526Sdavid.guillen@arm.com virtual void activateContext(ThreadID thread_num); 275393SN/A 276393SN/A /// Notify the CPU that the indicated context is now suspended. 27711526Sdavid.guillen@arm.com /// Check if possible to enter a lower power state 27811526Sdavid.guillen@arm.com virtual void suspendContext(ThreadID thread_num); 279393SN/A 280393SN/A /// Notify the CPU that the indicated context is now halted. 28112284Sjose.marinho@arm.com virtual void haltContext(ThreadID thread_num); 2822SN/A 2834000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2844000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2854000Ssaidi@eecs.umich.edu 2864000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2879652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2884000Ssaidi@eecs.umich.edu 28910030SAli.Saidi@ARM.com /// Get the number of thread contexts available 29010030SAli.Saidi@ARM.com unsigned numContexts() { return threadContexts.size(); } 29110030SAli.Saidi@ARM.com 29211435Smitch.hayenga@arm.com /// Convert ContextID to threadID 29311435Smitch.hayenga@arm.com ThreadID contextToThread(ContextID cid) 29411435Smitch.hayenga@arm.com { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); } 29511435Smitch.hayenga@arm.com 2962SN/A public: 2975529Snate@binkert.org typedef BaseCPUParams Params; 2985529Snate@binkert.org const Params *params() const 2995529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 3008876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 3011191SN/A virtual ~BaseCPU(); 3022SN/A 30311169Sandreas.hansson@arm.com void init() override; 30411169Sandreas.hansson@arm.com void startup() override; 30511169Sandreas.hansson@arm.com void regStats() override; 3062SN/A 30711168Sandreas.hansson@arm.com void regProbePoints() override; 30810464SAndreas.Sandberg@ARM.com 3092680Sktlim@umich.edu void registerThreadContexts(); 310180SN/A 31112276Sanouk.vanlaer@arm.com // Functions to deschedule and reschedule the events to enter the 31212276Sanouk.vanlaer@arm.com // power gating sleep before and after checkpoiting respectively. 31312276Sanouk.vanlaer@arm.com void deschedulePowerGatingEvent(); 31412276Sanouk.vanlaer@arm.com void schedulePowerGatingEvent(); 31512276Sanouk.vanlaer@arm.com 3169254SAndreas.Sandberg@arm.com /** 3179254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 3189254SAndreas.Sandberg@arm.com * 3199254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 3209254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 3219254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 3229254SAndreas.Sandberg@arm.com */ 3232798Sktlim@umich.edu virtual void switchOut(); 324180SN/A 3259254SAndreas.Sandberg@arm.com /** 3269254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 3279254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3289254SAndreas.Sandberg@arm.com * 3299254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3309254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3319254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3329254SAndreas.Sandberg@arm.com * CPU. 3339254SAndreas.Sandberg@arm.com * 3349254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3359254SAndreas.Sandberg@arm.com */ 3369254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 337180SN/A 338124SN/A /** 3399446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3409446SAndreas.Sandberg@ARM.com * 3419446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3429446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3439446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3449446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3459446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3469446SAndreas.Sandberg@ARM.com */ 3479446SAndreas.Sandberg@ARM.com void flushTLBs(); 3489446SAndreas.Sandberg@ARM.com 3499446SAndreas.Sandberg@ARM.com /** 3509430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3519430SAndreas.Sandberg@ARM.com * 3529430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3539430SAndreas.Sandberg@ARM.com */ 3549430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3559430SAndreas.Sandberg@ARM.com 3569430SAndreas.Sandberg@ARM.com /** 3579523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3589523SAndreas.Sandberg@ARM.com * CPU. 3599523SAndreas.Sandberg@ARM.com * 3609523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3619523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3629523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3639523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3649523SAndreas.Sandberg@ARM.com */ 3659523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3669523SAndreas.Sandberg@ARM.com 3679523SAndreas.Sandberg@ARM.com /** 368124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 369124SN/A * This is a constant for the duration of the simulation. 370124SN/A */ 3716221Snate@binkert.org ThreadID numThreads; 3722SN/A 373124SN/A /** 374124SN/A * Vector of per-thread instruction-based event queues. Used for 375124SN/A * scheduling events based on number of instructions committed by 376124SN/A * a particular thread. 377124SN/A */ 378503SN/A EventQueue **comInstEventQueue; 3792SN/A 380124SN/A /** 381124SN/A * Vector of per-thread load-based event queues. Used for 382124SN/A * scheduling events based on number of loads committed by 383124SN/A *a particular thread. 384124SN/A */ 385124SN/A EventQueue **comLoadEventQueue; 386124SN/A 3872SN/A System *system; 388921SN/A 389921SN/A /** 3909814Sandreas.hansson@arm.com * Get the cache line size of the system. 3919814Sandreas.hansson@arm.com */ 3929814Sandreas.hansson@arm.com inline unsigned int cacheLineSize() const { return _cacheLineSize; } 3939814Sandreas.hansson@arm.com 3949814Sandreas.hansson@arm.com /** 395921SN/A * Serialize this object to the given output stream. 3969448SAndreas.Sandberg@ARM.com * 3979448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 3989448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 3999448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 4009448SAndreas.Sandberg@ARM.com * reuse. 4019448SAndreas.Sandberg@ARM.com * 402921SN/A * @param os The stream to serialize to. 403921SN/A */ 40411168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 405921SN/A 406921SN/A /** 407921SN/A * Reconstruct the state of this object from a checkpoint. 4089448SAndreas.Sandberg@ARM.com * 4099448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 4109448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 4119448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 4129448SAndreas.Sandberg@ARM.com * promotes better code reuse. 4139448SAndreas.Sandberg@ARM.com 414921SN/A * @param cp The checkpoint use. 4159448SAndreas.Sandberg@ARM.com * @param section The section name of this object. 416921SN/A */ 41711168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 418921SN/A 419124SN/A /** 4209448SAndreas.Sandberg@ARM.com * Serialize a single thread. 4219448SAndreas.Sandberg@ARM.com * 4229448SAndreas.Sandberg@ARM.com * @param os The stream to serialize to. 4239448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4249448SAndreas.Sandberg@ARM.com */ 42510905Sandreas.sandberg@arm.com virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {}; 4269448SAndreas.Sandberg@ARM.com 4279448SAndreas.Sandberg@ARM.com /** 4289448SAndreas.Sandberg@ARM.com * Unserialize one thread. 4299448SAndreas.Sandberg@ARM.com * 4309448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 4319448SAndreas.Sandberg@ARM.com * @param section The section name of this thread. 4329448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4339448SAndreas.Sandberg@ARM.com */ 43410905Sandreas.sandberg@arm.com virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {}; 4359448SAndreas.Sandberg@ARM.com 4368834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 4378834Satgutier@umich.edu 4388834Satgutier@umich.edu virtual Counter totalOps() const = 0; 439707SN/A 4409749Sandreas@sandberg.pp.se /** 4419749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4429749Sandreas@sandberg.pp.se * predefined number of instructions. 4439749Sandreas@sandberg.pp.se * 4449749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4459749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4469749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4479749Sandreas@sandberg.pp.se * instructions rather than ticks. 4489749Sandreas@sandberg.pp.se * 4499749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4509749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4519749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4529749Sandreas@sandberg.pp.se */ 4539749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4549749Sandreas@sandberg.pp.se 4559749Sandreas@sandberg.pp.se /** 4569749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4579749Sandreas@sandberg.pp.se * predefined number of load operations. 4589749Sandreas@sandberg.pp.se * 4599749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4609749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4619749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4629749Sandreas@sandberg.pp.se * loads rather than ticks. 4639749Sandreas@sandberg.pp.se * 4649749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4659749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4669749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4679749Sandreas@sandberg.pp.se */ 4689749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4699749Sandreas@sandberg.pp.se 47011415SGeoffrey.Blake@arm.com /** 47111415SGeoffrey.Blake@arm.com * Get the number of instructions executed by the specified thread 47211415SGeoffrey.Blake@arm.com * on this CPU. Used by Python to control simulation. 47311415SGeoffrey.Blake@arm.com * 47411415SGeoffrey.Blake@arm.com * @param tid Thread monitor 47511415SGeoffrey.Blake@arm.com * @return Number of instructions executed 47611415SGeoffrey.Blake@arm.com */ 47711415SGeoffrey.Blake@arm.com uint64_t getCurrentInstCount(ThreadID tid); 47811415SGeoffrey.Blake@arm.com 47910464SAndreas.Sandberg@ARM.com public: 48010464SAndreas.Sandberg@ARM.com /** 48110464SAndreas.Sandberg@ARM.com * @{ 48210464SAndreas.Sandberg@ARM.com * @name PMU Probe points. 48310464SAndreas.Sandberg@ARM.com */ 48410464SAndreas.Sandberg@ARM.com 48510464SAndreas.Sandberg@ARM.com /** 48610464SAndreas.Sandberg@ARM.com * Helper method to trigger PMU probes for a committed 48710464SAndreas.Sandberg@ARM.com * instruction. 48810464SAndreas.Sandberg@ARM.com * 48910464SAndreas.Sandberg@ARM.com * @param inst Instruction that just committed 49010464SAndreas.Sandberg@ARM.com */ 49110464SAndreas.Sandberg@ARM.com virtual void probeInstCommit(const StaticInstPtr &inst); 49210464SAndreas.Sandberg@ARM.com 49312284Sjose.marinho@arm.com protected: 49410464SAndreas.Sandberg@ARM.com /** 49510464SAndreas.Sandberg@ARM.com * Helper method to instantiate probe points belonging to this 49610464SAndreas.Sandberg@ARM.com * object. 49710464SAndreas.Sandberg@ARM.com * 49810464SAndreas.Sandberg@ARM.com * @param name Name of the probe point. 49910464SAndreas.Sandberg@ARM.com * @return A unique_ptr to the new probe point. 50010464SAndreas.Sandberg@ARM.com */ 50110464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr pmuProbePoint(const char *name); 50210464SAndreas.Sandberg@ARM.com 50310464SAndreas.Sandberg@ARM.com /** 50410464SAndreas.Sandberg@ARM.com * Instruction commit probe point. 50510464SAndreas.Sandberg@ARM.com * 50610464SAndreas.Sandberg@ARM.com * This probe point is triggered whenever one or more instructions 50710464SAndreas.Sandberg@ARM.com * are committed. It is normally triggered once for every 50810464SAndreas.Sandberg@ARM.com * instruction. However, CPU models committing bundles of 50910464SAndreas.Sandberg@ARM.com * instructions may call notify once for the entire bundle. 51010464SAndreas.Sandberg@ARM.com */ 51110464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredInsts; 51210464SAndreas.Sandberg@ARM.com 51310464SAndreas.Sandberg@ARM.com /** Retired load instructions */ 51410464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredLoads; 51510464SAndreas.Sandberg@ARM.com /** Retired store instructions */ 51610464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredStores; 51710464SAndreas.Sandberg@ARM.com 51810464SAndreas.Sandberg@ARM.com /** Retired branches (any type) */ 51910464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredBranches; 52010464SAndreas.Sandberg@ARM.com 52112284Sjose.marinho@arm.com /** CPU cycle counter even if any thread Context is suspended*/ 52212284Sjose.marinho@arm.com ProbePoints::PMUUPtr ppAllCycles; 52312284Sjose.marinho@arm.com 52412284Sjose.marinho@arm.com /** CPU cycle counter, only counts if any thread contexts is active **/ 52512284Sjose.marinho@arm.com ProbePoints::PMUUPtr ppActiveCycles; 52612284Sjose.marinho@arm.com 52712284Sjose.marinho@arm.com /** 52812284Sjose.marinho@arm.com * ProbePoint that signals transitions of threadContexts sets. 52912284Sjose.marinho@arm.com * The ProbePoint reports information through it bool parameter. 53012284Sjose.marinho@arm.com * - If the parameter is true then the last enabled threadContext of the 53112284Sjose.marinho@arm.com * CPU object was disabled. 53212284Sjose.marinho@arm.com * - If the parameter is false then a threadContext was enabled, all the 53312284Sjose.marinho@arm.com * remaining threadContexts are disabled. 53412284Sjose.marinho@arm.com */ 53512284Sjose.marinho@arm.com ProbePointArg<bool> *ppSleeping; 53610464SAndreas.Sandberg@ARM.com /** @} */ 53710464SAndreas.Sandberg@ARM.com 53812284Sjose.marinho@arm.com enum CPUState { 53912284Sjose.marinho@arm.com CPU_STATE_ON, 54012284Sjose.marinho@arm.com CPU_STATE_SLEEP, 54112284Sjose.marinho@arm.com CPU_STATE_WAKEUP 54212284Sjose.marinho@arm.com }; 54310464SAndreas.Sandberg@ARM.com 54412284Sjose.marinho@arm.com Cycles previousCycle; 54512284Sjose.marinho@arm.com CPUState previousState; 54612284Sjose.marinho@arm.com 54712284Sjose.marinho@arm.com /** base method keeping track of cycle progression **/ 54812284Sjose.marinho@arm.com inline void updateCycleCounters(CPUState state) 54912284Sjose.marinho@arm.com { 55012284Sjose.marinho@arm.com uint32_t delta = curCycle() - previousCycle; 55112284Sjose.marinho@arm.com 55212284Sjose.marinho@arm.com if (previousState == CPU_STATE_ON) { 55312284Sjose.marinho@arm.com ppActiveCycles->notify(delta); 55412284Sjose.marinho@arm.com } 55512284Sjose.marinho@arm.com 55612284Sjose.marinho@arm.com switch (state) 55712284Sjose.marinho@arm.com { 55812284Sjose.marinho@arm.com case CPU_STATE_WAKEUP: 55912284Sjose.marinho@arm.com ppSleeping->notify(false); 56012284Sjose.marinho@arm.com break; 56112284Sjose.marinho@arm.com case CPU_STATE_SLEEP: 56212284Sjose.marinho@arm.com ppSleeping->notify(true); 56312284Sjose.marinho@arm.com break; 56412284Sjose.marinho@arm.com default: 56512284Sjose.marinho@arm.com break; 56612284Sjose.marinho@arm.com } 56712284Sjose.marinho@arm.com 56812284Sjose.marinho@arm.com ppAllCycles->notify(delta); 56912284Sjose.marinho@arm.com 57012284Sjose.marinho@arm.com previousCycle = curCycle(); 57112284Sjose.marinho@arm.com previousState = state; 57212284Sjose.marinho@arm.com } 57310464SAndreas.Sandberg@ARM.com 5741191SN/A // Function tracing 5751191SN/A private: 5761191SN/A bool functionTracingEnabled; 5771191SN/A std::ostream *functionTraceStream; 5781191SN/A Addr currentFunctionStart; 5791191SN/A Addr currentFunctionEnd; 5801191SN/A Tick functionEntryTick; 5811191SN/A void enableFunctionTrace(); 5821191SN/A void traceFunctionsInternal(Addr pc); 5831191SN/A 5848662SAli.Saidi@ARM.com private: 5858662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 5868662SAli.Saidi@ARM.com 5878662SAli.Saidi@ARM.com public: 5881191SN/A void traceFunctions(Addr pc) 5891191SN/A { 5901191SN/A if (functionTracingEnabled) 5911191SN/A traceFunctionsInternal(pc); 5921191SN/A } 5931191SN/A 5942SN/A static int numSimulatedCPUs() { return cpuList.size(); } 5958834Satgutier@umich.edu static Counter numSimulatedInsts() 596707SN/A { 597707SN/A Counter total = 0; 598707SN/A 599707SN/A int size = cpuList.size(); 600707SN/A for (int i = 0; i < size; ++i) 6018834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 6028834Satgutier@umich.edu 6038834Satgutier@umich.edu return total; 6048834Satgutier@umich.edu } 6058834Satgutier@umich.edu 6068834Satgutier@umich.edu static Counter numSimulatedOps() 6078834Satgutier@umich.edu { 6088834Satgutier@umich.edu Counter total = 0; 6098834Satgutier@umich.edu 6108834Satgutier@umich.edu int size = cpuList.size(); 6118834Satgutier@umich.edu for (int i = 0; i < size; ++i) 6128834Satgutier@umich.edu total += cpuList[i]->totalOps(); 613707SN/A 614707SN/A return total; 615707SN/A } 616707SN/A 617707SN/A public: 618707SN/A // Number of CPU cycles simulated 6195999Snate@binkert.org Stats::Scalar numCycles; 6207914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 6217914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 62210529Smorr@cs.wisc.edu 62310529Smorr@cs.wisc.edu private: 62411148Smitch.hayenga@arm.com std::vector<AddressMonitor> addressMonitor; 62510529Smorr@cs.wisc.edu 62610529Smorr@cs.wisc.edu public: 62711148Smitch.hayenga@arm.com void armMonitor(ThreadID tid, Addr address); 62811148Smitch.hayenga@arm.com bool mwait(ThreadID tid, PacketPtr pkt); 62912406Sgabeblack@google.com void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb); 63011148Smitch.hayenga@arm.com AddressMonitor *getCpuAddrMonitor(ThreadID tid) 63111148Smitch.hayenga@arm.com { 63211148Smitch.hayenga@arm.com assert(tid < numThreads); 63311148Smitch.hayenga@arm.com return &addressMonitor[tid]; 63411148Smitch.hayenga@arm.com } 63511877Sbrandon.potter@amd.com 63612122Sjose.marinho@arm.com bool waitForRemoteGDB() const; 63712122Sjose.marinho@arm.com 63811877Sbrandon.potter@amd.com Cycles syscallRetryLatency; 63912277Sjose.marinho@arm.com 64012276Sanouk.vanlaer@arm.com // Enables CPU to enter power gating on a configurable cycle count 64112276Sanouk.vanlaer@arm.com protected: 64212277Sjose.marinho@arm.com void enterPwrGating(); 64312277Sjose.marinho@arm.com 64412276Sanouk.vanlaer@arm.com const Cycles pwrGatingLatency; 64512277Sjose.marinho@arm.com const bool powerGatingOnIdle; 64612276Sanouk.vanlaer@arm.com EventFunctionWrapper enterPwrGatingEvent; 6472SN/A}; 6482SN/A 6499850Sandreas.hansson@arm.com#endif // THE_ISA == NULL_ISA 6509850Sandreas.hansson@arm.com 6511717SN/A#endif // __CPU_BASE_HH__ 652