base.hh revision 1191 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __BASE_CPU_HH__
30#define __BASE_CPU_HH__
31
32#include <vector>
33
34#include "base/statistics.hh"
35#include "sim/eventq.hh"
36#include "sim/sim_object.hh"
37#include "targetarch/isa_traits.hh"
38
39#ifdef FULL_SYSTEM
40class System;
41#endif
42
43class BranchPred;
44class ExecContext;
45
46class BaseCPU : public SimObject
47{
48#ifdef FULL_SYSTEM
49  protected:
50    Tick frequency;
51    uint64_t interrupts[NumInterruptLevels];
52    uint64_t intstatus;
53
54  public:
55    virtual void post_interrupt(int int_num, int index);
56    virtual void clear_interrupt(int int_num, int index);
57    virtual void clear_interrupts();
58    bool checkInterrupts;
59
60    bool check_interrupt(int int_num) const {
61        if (int_num > NumInterruptLevels)
62            panic("int_num out of bounds\n");
63
64        return interrupts[int_num] != 0;
65    }
66
67    bool check_interrupts() const { return intstatus != 0; }
68    uint64_t intr_status() const { return intstatus; }
69
70    Tick getFreq() const { return frequency; }
71#endif
72
73  protected:
74    std::vector<ExecContext *> execContexts;
75
76  public:
77
78    /// Notify the CPU that the indicated context is now active.  The
79    /// delay parameter indicates the number of ticks to wait before
80    /// executing (typically 0 or 1).
81    virtual void activateContext(int thread_num, int delay) {}
82
83    /// Notify the CPU that the indicated context is now suspended.
84    virtual void suspendContext(int thread_num) {}
85
86    /// Notify the CPU that the indicated context is now deallocated.
87    virtual void deallocateContext(int thread_num) {}
88
89    /// Notify the CPU that the indicated context is now halted.
90    virtual void haltContext(int thread_num) {}
91
92  public:
93
94#ifdef FULL_SYSTEM
95    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
96            Counter max_insts_any_thread, Counter max_insts_all_threads,
97            Counter max_loads_any_thread, Counter max_loads_all_threads,
98            System *_system, Tick freq,
99            bool _function_trace = false, Tick _function_trace_start = 0);
100#else
101    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
102            Counter max_insts_any_thread = 0,
103            Counter max_insts_all_threads = 0,
104            Counter max_loads_any_thread = 0,
105            Counter max_loads_all_threads = 0,
106            bool _function_trace = false, Tick _function_trace_start = 0);
107#endif
108
109    virtual ~BaseCPU();
110
111    virtual void init();
112    virtual void regStats();
113
114    bool deferRegistration;
115    void registerExecContexts();
116
117    /// Prepare for another CPU to take over execution.  Called by
118    /// takeOverFrom() on its argument.
119    virtual void switchOut();
120
121    /// Take over execution from the given CPU.  Used for warm-up and
122    /// sampling.
123    virtual void takeOverFrom(BaseCPU *);
124
125    /**
126     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
127     * This is a constant for the duration of the simulation.
128     */
129    int number_of_threads;
130
131    /**
132     * Vector of per-thread instruction-based event queues.  Used for
133     * scheduling events based on number of instructions committed by
134     * a particular thread.
135     */
136    EventQueue **comInstEventQueue;
137
138    /**
139     * Vector of per-thread load-based event queues.  Used for
140     * scheduling events based on number of loads committed by
141     *a particular thread.
142     */
143    EventQueue **comLoadEventQueue;
144
145#ifdef FULL_SYSTEM
146    System *system;
147
148    /**
149     * Serialize this object to the given output stream.
150     * @param os The stream to serialize to.
151     */
152    virtual void serialize(std::ostream &os);
153
154    /**
155     * Reconstruct the state of this object from a checkpoint.
156     * @param cp The checkpoint use.
157     * @param section The section name of this object
158     */
159    virtual void unserialize(Checkpoint *cp, const std::string &section);
160
161#endif
162
163    /**
164     * Return pointer to CPU's branch predictor (NULL if none).
165     * @return Branch predictor pointer.
166     */
167    virtual BranchPred *getBranchPred() { return NULL; };
168
169    virtual Counter totalInstructions() const { return 0; }
170
171    // Function tracing
172  private:
173    bool functionTracingEnabled;
174    std::ostream *functionTraceStream;
175    Addr currentFunctionStart;
176    Addr currentFunctionEnd;
177    Tick functionEntryTick;
178    void enableFunctionTrace();
179    void traceFunctionsInternal(Addr pc);
180
181  protected:
182    void traceFunctions(Addr pc)
183    {
184        if (functionTracingEnabled)
185            traceFunctionsInternal(pc);
186    }
187
188  private:
189    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
190
191  public:
192    static int numSimulatedCPUs() { return cpuList.size(); }
193    static Counter numSimulatedInstructions()
194    {
195        Counter total = 0;
196
197        int size = cpuList.size();
198        for (int i = 0; i < size; ++i)
199            total += cpuList[i]->totalInstructions();
200
201        return total;
202    }
203
204  public:
205    // Number of CPU cycles simulated
206    Stats::Scalar<> numCycles;
207};
208
209#endif // __BASE_CPU_HH__
210