base.hh revision 10905
12SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 519850Sandreas.hansson@arm.com// Before we do anything else, check if this build is the NULL ISA, 529850Sandreas.hansson@arm.com// and if so stop here 539850Sandreas.hansson@arm.com#include "config/the_isa.hh" 549850Sandreas.hansson@arm.com#if THE_ISA == NULL_ISA 559850Sandreas.hansson@arm.com#include "arch/null/cpu_dummy.hh" 569850Sandreas.hansson@arm.com#else 578745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 584182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 595664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 60707SN/A#include "base/statistics.hh" 618229Snate@binkert.org#include "mem/mem_object.hh" 6256SN/A#include "sim/eventq.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 644776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 6510464SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 669814Sandreas.hansson@arm.com#include "sim/system.hh" 6710529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 682SN/A 6910529Smorr@cs.wisc.educlass BaseCPU; 708901Sandreas.hansson@arm.comstruct BaseCPUParams; 712315SN/Aclass CheckerCPU; 722680Sktlim@umich.educlass ThreadContext; 732SN/A 7410529Smorr@cs.wisc.edustruct AddressMonitor 7510529Smorr@cs.wisc.edu{ 7610529Smorr@cs.wisc.edu AddressMonitor(); 7710529Smorr@cs.wisc.edu bool doMonitor(PacketPtr pkt); 7810529Smorr@cs.wisc.edu 7910529Smorr@cs.wisc.edu bool armed; 8010529Smorr@cs.wisc.edu Addr vAddr; 8110529Smorr@cs.wisc.edu Addr pAddr; 8210529Smorr@cs.wisc.edu uint64_t val; 8310529Smorr@cs.wisc.edu bool waiting; // 0=normal, 1=mwaiting 8410529Smorr@cs.wisc.edu bool gotWakeup; 8510529Smorr@cs.wisc.edu}; 8610529Smorr@cs.wisc.edu 872356SN/Aclass CPUProgressEvent : public Event 882356SN/A{ 892356SN/A protected: 906144Sksewell@umich.edu Tick _interval; 912356SN/A Counter lastNumInst; 922356SN/A BaseCPU *cpu; 936144Sksewell@umich.edu bool _repeatEvent; 942356SN/A 952356SN/A public: 966144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 972356SN/A 982356SN/A void process(); 992356SN/A 1006144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 1016144Sksewell@umich.edu Tick interval() { return _interval; } 1026144Sksewell@umich.edu 1036144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 1046144Sksewell@umich.edu 1055336Shines@cs.fsu.edu virtual const char *description() const; 1062356SN/A}; 1072356SN/A 1082856Srdreslin@umich.educlass BaseCPU : public MemObject 1092SN/A{ 1101634SN/A protected: 1119157Sandreas.hansson@arm.com 11210662SAli.Saidi@ARM.com /// Instruction count used for SPARC misc register 11310662SAli.Saidi@ARM.com /// @todo unify this with the counters that cpus individually keep 1143814Ssaidi@eecs.umich.edu Tick instCnt; 11510662SAli.Saidi@ARM.com 1165712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1175712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1185715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1195712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1205712Shsul@eecs.umich.edu int _cpuId; 1211634SN/A 12210190Sakash.bagdia@arm.com /** Each cpu will have a socket ID that corresponds to its physical location 12310190Sakash.bagdia@arm.com * in the system. This is usually used to bucket cpu cores under single DVFS 12410190Sakash.bagdia@arm.com * domain. This information may also be required by the OS to identify the 12510190Sakash.bagdia@arm.com * cpu core grouping (as in the case of ARM via MPIDR register) 12610190Sakash.bagdia@arm.com */ 12710190Sakash.bagdia@arm.com const uint32_t _socketId; 12810190Sakash.bagdia@arm.com 1298832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1308832SAli.Saidi@ARM.com MasterID _instMasterId; 1318832SAli.Saidi@ARM.com 1328832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1338832SAli.Saidi@ARM.com MasterID _dataMasterId; 1348832SAli.Saidi@ARM.com 1359332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1369332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1379332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1389332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1399332Sdam.sunwoo@arm.com */ 1409332Sdam.sunwoo@arm.com uint32_t _taskId; 1419332Sdam.sunwoo@arm.com 1429332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1439332Sdam.sunwoo@arm.com * used to generate a taskId */ 1449332Sdam.sunwoo@arm.com uint32_t _pid; 1459332Sdam.sunwoo@arm.com 1469430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1479430SAndreas.Sandberg@ARM.com bool _switchedOut; 1489430SAndreas.Sandberg@ARM.com 1499814Sandreas.hansson@arm.com /** Cache the cache line size that we get from the system */ 1509814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 1519814Sandreas.hansson@arm.com 1521634SN/A public: 1538850Sandreas.hansson@arm.com 1548850Sandreas.hansson@arm.com /** 1558850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1568850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1578850Sandreas.hansson@arm.com * 1588850Sandreas.hansson@arm.com * @return a reference to the data port 1598850Sandreas.hansson@arm.com */ 1609608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1618850Sandreas.hansson@arm.com 1628850Sandreas.hansson@arm.com /** 1638850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1648850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1658850Sandreas.hansson@arm.com * 1668850Sandreas.hansson@arm.com * @return a reference to the instruction port 1678850Sandreas.hansson@arm.com */ 1689608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1698850Sandreas.hansson@arm.com 1705712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 17110110Sandreas.hansson@arm.com int cpuId() const { return _cpuId; } 1725712Shsul@eecs.umich.edu 17310190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 17410190Sakash.bagdia@arm.com uint32_t socketId() const { return _socketId; } 17510190Sakash.bagdia@arm.com 1768832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1778832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1788832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1798832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1808832SAli.Saidi@ARM.com 1818850Sandreas.hansson@arm.com /** 1828926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1838926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1848926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1858850Sandreas.hansson@arm.com * 1868850Sandreas.hansson@arm.com * @param if_name the port name 1878850Sandreas.hansson@arm.com * @param idx ignored index 1888850Sandreas.hansson@arm.com * 1898922Swilliam.wang@arm.com * @return a reference to the port with the given name 1908850Sandreas.hansson@arm.com */ 1919294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1929294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1938850Sandreas.hansson@arm.com 1949332Sdam.sunwoo@arm.com /** Get cpu task id */ 1959332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1969332Sdam.sunwoo@arm.com /** Set cpu task id */ 1979332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1989332Sdam.sunwoo@arm.com 1999332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 2009332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 2019332Sdam.sunwoo@arm.com 2027914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 2037914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 2043814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 2053814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 2061634SN/A 2075664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 2085664Sgblack@eecs.umich.edu 2092SN/A protected: 2105704Snate@binkert.org TheISA::Interrupts *interrupts; 2112SN/A 2122SN/A public: 2135645Sgblack@eecs.umich.edu TheISA::Interrupts * 2145645Sgblack@eecs.umich.edu getInterruptController() 2155645Sgblack@eecs.umich.edu { 2165647Sgblack@eecs.umich.edu return interrupts; 2175645Sgblack@eecs.umich.edu } 2185645Sgblack@eecs.umich.edu 2195807Snate@binkert.org virtual void wakeup() = 0; 2205807Snate@binkert.org 2215807Snate@binkert.org void 2225807Snate@binkert.org postInterrupt(int int_num, int index) 2235807Snate@binkert.org { 2245807Snate@binkert.org interrupts->post(int_num, index); 2258779Sgblack@eecs.umich.edu if (FullSystem) 2268779Sgblack@eecs.umich.edu wakeup(); 2275807Snate@binkert.org } 2285807Snate@binkert.org 2295807Snate@binkert.org void 2305807Snate@binkert.org clearInterrupt(int int_num, int index) 2315807Snate@binkert.org { 2325807Snate@binkert.org interrupts->clear(int_num, index); 2335807Snate@binkert.org } 2345807Snate@binkert.org 2355807Snate@binkert.org void 2365807Snate@binkert.org clearInterrupts() 2375807Snate@binkert.org { 2385807Snate@binkert.org interrupts->clearAll(); 2395807Snate@binkert.org } 2402SN/A 2415704Snate@binkert.org bool 2425704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2435704Snate@binkert.org { 2448793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2455704Snate@binkert.org } 2461917SN/A 2471917SN/A class ProfileEvent : public Event 2481917SN/A { 2491917SN/A private: 2501917SN/A BaseCPU *cpu; 2515536Srstrong@hp.com Tick interval; 2521917SN/A 2531917SN/A public: 2545536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2551917SN/A void process(); 2561917SN/A }; 2571917SN/A ProfileEvent *profileEvent; 2582SN/A 2592SN/A protected: 2602680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2612SN/A 2624776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2634776Sgblack@eecs.umich.edu 2642SN/A public: 265393SN/A 2667764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2677764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2687764Sgblack@eecs.umich.edu 2694776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2704776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2714776Sgblack@eecs.umich.edu 27210407Smitch.hayenga@arm.com /// Notify the CPU that the indicated context is now active. 27310407Smitch.hayenga@arm.com virtual void activateContext(ThreadID thread_num) {} 274393SN/A 275393SN/A /// Notify the CPU that the indicated context is now suspended. 2768737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 277393SN/A 278393SN/A /// Notify the CPU that the indicated context is now halted. 2798737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2802SN/A 2814000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2824000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2834000Ssaidi@eecs.umich.edu 2844000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2859652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2864000Ssaidi@eecs.umich.edu 28710030SAli.Saidi@ARM.com /// Get the number of thread contexts available 28810030SAli.Saidi@ARM.com unsigned numContexts() { return threadContexts.size(); } 28910030SAli.Saidi@ARM.com 2902SN/A public: 2915529Snate@binkert.org typedef BaseCPUParams Params; 2925529Snate@binkert.org const Params *params() const 2935529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2948876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2951191SN/A virtual ~BaseCPU(); 2962SN/A 2971129SN/A virtual void init(); 2981917SN/A virtual void startup(); 2992SN/A virtual void regStats(); 3002SN/A 30110464SAndreas.Sandberg@ARM.com void regProbePoints() M5_ATTR_OVERRIDE; 30210464SAndreas.Sandberg@ARM.com 3032680Sktlim@umich.edu void registerThreadContexts(); 304180SN/A 3059254SAndreas.Sandberg@arm.com /** 3069254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 3079254SAndreas.Sandberg@arm.com * 3089254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 3099254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 3109254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 3119254SAndreas.Sandberg@arm.com */ 3122798Sktlim@umich.edu virtual void switchOut(); 313180SN/A 3149254SAndreas.Sandberg@arm.com /** 3159254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 3169254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3179254SAndreas.Sandberg@arm.com * 3189254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3199254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3209254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3219254SAndreas.Sandberg@arm.com * CPU. 3229254SAndreas.Sandberg@arm.com * 3239254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3249254SAndreas.Sandberg@arm.com */ 3259254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 326180SN/A 327124SN/A /** 3289446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3299446SAndreas.Sandberg@ARM.com * 3309446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3319446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3329446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3339446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3349446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3359446SAndreas.Sandberg@ARM.com */ 3369446SAndreas.Sandberg@ARM.com void flushTLBs(); 3379446SAndreas.Sandberg@ARM.com 3389446SAndreas.Sandberg@ARM.com /** 3399430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3409430SAndreas.Sandberg@ARM.com * 3419430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3429430SAndreas.Sandberg@ARM.com */ 3439430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3449430SAndreas.Sandberg@ARM.com 3459430SAndreas.Sandberg@ARM.com /** 3469523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3479523SAndreas.Sandberg@ARM.com * CPU. 3489523SAndreas.Sandberg@ARM.com * 3499523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3509523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3519523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3529523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3539523SAndreas.Sandberg@ARM.com */ 3549523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3559523SAndreas.Sandberg@ARM.com 3569523SAndreas.Sandberg@ARM.com /** 357124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 358124SN/A * This is a constant for the duration of the simulation. 359124SN/A */ 3606221Snate@binkert.org ThreadID numThreads; 3612SN/A 362124SN/A /** 363124SN/A * Vector of per-thread instruction-based event queues. Used for 364124SN/A * scheduling events based on number of instructions committed by 365124SN/A * a particular thread. 366124SN/A */ 367503SN/A EventQueue **comInstEventQueue; 3682SN/A 369124SN/A /** 370124SN/A * Vector of per-thread load-based event queues. Used for 371124SN/A * scheduling events based on number of loads committed by 372124SN/A *a particular thread. 373124SN/A */ 374124SN/A EventQueue **comLoadEventQueue; 375124SN/A 3762SN/A System *system; 377921SN/A 378921SN/A /** 3799814Sandreas.hansson@arm.com * Get the cache line size of the system. 3809814Sandreas.hansson@arm.com */ 3819814Sandreas.hansson@arm.com inline unsigned int cacheLineSize() const { return _cacheLineSize; } 3829814Sandreas.hansson@arm.com 3839814Sandreas.hansson@arm.com /** 384921SN/A * Serialize this object to the given output stream. 3859448SAndreas.Sandberg@ARM.com * 3869448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 3879448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 3889448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 3899448SAndreas.Sandberg@ARM.com * reuse. 3909448SAndreas.Sandberg@ARM.com * 391921SN/A * @param os The stream to serialize to. 392921SN/A */ 39310905Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 394921SN/A 395921SN/A /** 396921SN/A * Reconstruct the state of this object from a checkpoint. 3979448SAndreas.Sandberg@ARM.com * 3989448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 3999448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 4009448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 4019448SAndreas.Sandberg@ARM.com * promotes better code reuse. 4029448SAndreas.Sandberg@ARM.com 403921SN/A * @param cp The checkpoint use. 4049448SAndreas.Sandberg@ARM.com * @param section The section name of this object. 405921SN/A */ 40610905Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 407921SN/A 408124SN/A /** 4099448SAndreas.Sandberg@ARM.com * Serialize a single thread. 4109448SAndreas.Sandberg@ARM.com * 4119448SAndreas.Sandberg@ARM.com * @param os The stream to serialize to. 4129448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4139448SAndreas.Sandberg@ARM.com */ 41410905Sandreas.sandberg@arm.com virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {}; 4159448SAndreas.Sandberg@ARM.com 4169448SAndreas.Sandberg@ARM.com /** 4179448SAndreas.Sandberg@ARM.com * Unserialize one thread. 4189448SAndreas.Sandberg@ARM.com * 4199448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 4209448SAndreas.Sandberg@ARM.com * @param section The section name of this thread. 4219448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4229448SAndreas.Sandberg@ARM.com */ 42310905Sandreas.sandberg@arm.com virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {}; 4249448SAndreas.Sandberg@ARM.com 4258834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 4268834Satgutier@umich.edu 4278834Satgutier@umich.edu virtual Counter totalOps() const = 0; 428707SN/A 4299749Sandreas@sandberg.pp.se /** 4309749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4319749Sandreas@sandberg.pp.se * predefined number of instructions. 4329749Sandreas@sandberg.pp.se * 4339749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4349749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4359749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4369749Sandreas@sandberg.pp.se * instructions rather than ticks. 4379749Sandreas@sandberg.pp.se * 4389749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4399749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4409749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4419749Sandreas@sandberg.pp.se */ 4429749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4439749Sandreas@sandberg.pp.se 4449749Sandreas@sandberg.pp.se /** 4459749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4469749Sandreas@sandberg.pp.se * predefined number of load operations. 4479749Sandreas@sandberg.pp.se * 4489749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4499749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4509749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4519749Sandreas@sandberg.pp.se * loads rather than ticks. 4529749Sandreas@sandberg.pp.se * 4539749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4549749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4559749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4569749Sandreas@sandberg.pp.se */ 4579749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4589749Sandreas@sandberg.pp.se 45910464SAndreas.Sandberg@ARM.com public: 46010464SAndreas.Sandberg@ARM.com /** 46110464SAndreas.Sandberg@ARM.com * @{ 46210464SAndreas.Sandberg@ARM.com * @name PMU Probe points. 46310464SAndreas.Sandberg@ARM.com */ 46410464SAndreas.Sandberg@ARM.com 46510464SAndreas.Sandberg@ARM.com /** 46610464SAndreas.Sandberg@ARM.com * Helper method to trigger PMU probes for a committed 46710464SAndreas.Sandberg@ARM.com * instruction. 46810464SAndreas.Sandberg@ARM.com * 46910464SAndreas.Sandberg@ARM.com * @param inst Instruction that just committed 47010464SAndreas.Sandberg@ARM.com */ 47110464SAndreas.Sandberg@ARM.com virtual void probeInstCommit(const StaticInstPtr &inst); 47210464SAndreas.Sandberg@ARM.com 47310464SAndreas.Sandberg@ARM.com /** 47410464SAndreas.Sandberg@ARM.com * Helper method to instantiate probe points belonging to this 47510464SAndreas.Sandberg@ARM.com * object. 47610464SAndreas.Sandberg@ARM.com * 47710464SAndreas.Sandberg@ARM.com * @param name Name of the probe point. 47810464SAndreas.Sandberg@ARM.com * @return A unique_ptr to the new probe point. 47910464SAndreas.Sandberg@ARM.com */ 48010464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr pmuProbePoint(const char *name); 48110464SAndreas.Sandberg@ARM.com 48210464SAndreas.Sandberg@ARM.com /** CPU cycle counter */ 48310464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppCycles; 48410464SAndreas.Sandberg@ARM.com 48510464SAndreas.Sandberg@ARM.com /** 48610464SAndreas.Sandberg@ARM.com * Instruction commit probe point. 48710464SAndreas.Sandberg@ARM.com * 48810464SAndreas.Sandberg@ARM.com * This probe point is triggered whenever one or more instructions 48910464SAndreas.Sandberg@ARM.com * are committed. It is normally triggered once for every 49010464SAndreas.Sandberg@ARM.com * instruction. However, CPU models committing bundles of 49110464SAndreas.Sandberg@ARM.com * instructions may call notify once for the entire bundle. 49210464SAndreas.Sandberg@ARM.com */ 49310464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredInsts; 49410464SAndreas.Sandberg@ARM.com 49510464SAndreas.Sandberg@ARM.com /** Retired load instructions */ 49610464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredLoads; 49710464SAndreas.Sandberg@ARM.com /** Retired store instructions */ 49810464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredStores; 49910464SAndreas.Sandberg@ARM.com 50010464SAndreas.Sandberg@ARM.com /** Retired branches (any type) */ 50110464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredBranches; 50210464SAndreas.Sandberg@ARM.com 50310464SAndreas.Sandberg@ARM.com /** @} */ 50410464SAndreas.Sandberg@ARM.com 50510464SAndreas.Sandberg@ARM.com 50610464SAndreas.Sandberg@ARM.com 5071191SN/A // Function tracing 5081191SN/A private: 5091191SN/A bool functionTracingEnabled; 5101191SN/A std::ostream *functionTraceStream; 5111191SN/A Addr currentFunctionStart; 5121191SN/A Addr currentFunctionEnd; 5131191SN/A Tick functionEntryTick; 5141191SN/A void enableFunctionTrace(); 5151191SN/A void traceFunctionsInternal(Addr pc); 5161191SN/A 5178662SAli.Saidi@ARM.com private: 5188662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 5198662SAli.Saidi@ARM.com 5208662SAli.Saidi@ARM.com public: 5211191SN/A void traceFunctions(Addr pc) 5221191SN/A { 5231191SN/A if (functionTracingEnabled) 5241191SN/A traceFunctionsInternal(pc); 5251191SN/A } 5261191SN/A 5272SN/A static int numSimulatedCPUs() { return cpuList.size(); } 5288834Satgutier@umich.edu static Counter numSimulatedInsts() 529707SN/A { 530707SN/A Counter total = 0; 531707SN/A 532707SN/A int size = cpuList.size(); 533707SN/A for (int i = 0; i < size; ++i) 5348834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 5358834Satgutier@umich.edu 5368834Satgutier@umich.edu return total; 5378834Satgutier@umich.edu } 5388834Satgutier@umich.edu 5398834Satgutier@umich.edu static Counter numSimulatedOps() 5408834Satgutier@umich.edu { 5418834Satgutier@umich.edu Counter total = 0; 5428834Satgutier@umich.edu 5438834Satgutier@umich.edu int size = cpuList.size(); 5448834Satgutier@umich.edu for (int i = 0; i < size; ++i) 5458834Satgutier@umich.edu total += cpuList[i]->totalOps(); 546707SN/A 547707SN/A return total; 548707SN/A } 549707SN/A 550707SN/A public: 551707SN/A // Number of CPU cycles simulated 5525999Snate@binkert.org Stats::Scalar numCycles; 5537914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 5547914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 55510529Smorr@cs.wisc.edu 55610529Smorr@cs.wisc.edu private: 55710529Smorr@cs.wisc.edu AddressMonitor addressMonitor; 55810529Smorr@cs.wisc.edu 55910529Smorr@cs.wisc.edu public: 56010529Smorr@cs.wisc.edu void armMonitor(Addr address); 56110529Smorr@cs.wisc.edu bool mwait(PacketPtr pkt); 56210529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb); 56310529Smorr@cs.wisc.edu AddressMonitor *getCpuAddrMonitor() { return &addressMonitor; } 56410529Smorr@cs.wisc.edu void atomicNotify(Addr address); 5652SN/A}; 5662SN/A 5679850Sandreas.hansson@arm.com#endif // THE_ISA == NULL_ISA 5689850Sandreas.hansson@arm.com 5691717SN/A#endif // __CPU_BASE_HH__ 570