base.hh revision 10190
12SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 519850Sandreas.hansson@arm.com// Before we do anything else, check if this build is the NULL ISA, 529850Sandreas.hansson@arm.com// and if so stop here 539850Sandreas.hansson@arm.com#include "config/the_isa.hh" 549850Sandreas.hansson@arm.com#if THE_ISA == NULL_ISA 559850Sandreas.hansson@arm.com#include "arch/null/cpu_dummy.hh" 569850Sandreas.hansson@arm.com#else 578745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 584182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 595664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 60707SN/A#include "base/statistics.hh" 618229Snate@binkert.org#include "mem/mem_object.hh" 6256SN/A#include "sim/eventq.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 644776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 659814Sandreas.hansson@arm.com#include "sim/system.hh" 662SN/A 678901Sandreas.hansson@arm.comstruct BaseCPUParams; 682315SN/Aclass CheckerCPU; 692680Sktlim@umich.educlass ThreadContext; 702SN/A 712356SN/Aclass CPUProgressEvent : public Event 722356SN/A{ 732356SN/A protected: 746144Sksewell@umich.edu Tick _interval; 752356SN/A Counter lastNumInst; 762356SN/A BaseCPU *cpu; 776144Sksewell@umich.edu bool _repeatEvent; 782356SN/A 792356SN/A public: 806144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 812356SN/A 822356SN/A void process(); 832356SN/A 846144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 856144Sksewell@umich.edu Tick interval() { return _interval; } 866144Sksewell@umich.edu 876144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 886144Sksewell@umich.edu 895336Shines@cs.fsu.edu virtual const char *description() const; 902356SN/A}; 912356SN/A 922856Srdreslin@umich.educlass BaseCPU : public MemObject 932SN/A{ 941634SN/A protected: 959157Sandreas.hansson@arm.com 963814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 973814Ssaidi@eecs.umich.edu Tick instCnt; 985712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 995712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1005715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1015712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1025712Shsul@eecs.umich.edu int _cpuId; 1031634SN/A 10410190Sakash.bagdia@arm.com /** Each cpu will have a socket ID that corresponds to its physical location 10510190Sakash.bagdia@arm.com * in the system. This is usually used to bucket cpu cores under single DVFS 10610190Sakash.bagdia@arm.com * domain. This information may also be required by the OS to identify the 10710190Sakash.bagdia@arm.com * cpu core grouping (as in the case of ARM via MPIDR register) 10810190Sakash.bagdia@arm.com */ 10910190Sakash.bagdia@arm.com const uint32_t _socketId; 11010190Sakash.bagdia@arm.com 1118832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1128832SAli.Saidi@ARM.com MasterID _instMasterId; 1138832SAli.Saidi@ARM.com 1148832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1158832SAli.Saidi@ARM.com MasterID _dataMasterId; 1168832SAli.Saidi@ARM.com 1179332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1189332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1199332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1209332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1219332Sdam.sunwoo@arm.com */ 1229332Sdam.sunwoo@arm.com uint32_t _taskId; 1239332Sdam.sunwoo@arm.com 1249332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1259332Sdam.sunwoo@arm.com * used to generate a taskId */ 1269332Sdam.sunwoo@arm.com uint32_t _pid; 1279332Sdam.sunwoo@arm.com 1289430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1299430SAndreas.Sandberg@ARM.com bool _switchedOut; 1309430SAndreas.Sandberg@ARM.com 1319814Sandreas.hansson@arm.com /** Cache the cache line size that we get from the system */ 1329814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 1339814Sandreas.hansson@arm.com 1341634SN/A public: 1358850Sandreas.hansson@arm.com 1368850Sandreas.hansson@arm.com /** 1378850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1388850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1398850Sandreas.hansson@arm.com * 1408850Sandreas.hansson@arm.com * @return a reference to the data port 1418850Sandreas.hansson@arm.com */ 1429608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1438850Sandreas.hansson@arm.com 1448850Sandreas.hansson@arm.com /** 1458850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1468850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1478850Sandreas.hansson@arm.com * 1488850Sandreas.hansson@arm.com * @return a reference to the instruction port 1498850Sandreas.hansson@arm.com */ 1509608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1518850Sandreas.hansson@arm.com 1525712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 15310110Sandreas.hansson@arm.com int cpuId() const { return _cpuId; } 1545712Shsul@eecs.umich.edu 15510190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 15610190Sakash.bagdia@arm.com uint32_t socketId() const { return _socketId; } 15710190Sakash.bagdia@arm.com 1588832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1598832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1608832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1618832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1628832SAli.Saidi@ARM.com 1638850Sandreas.hansson@arm.com /** 1648926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1658926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1668926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1678850Sandreas.hansson@arm.com * 1688850Sandreas.hansson@arm.com * @param if_name the port name 1698850Sandreas.hansson@arm.com * @param idx ignored index 1708850Sandreas.hansson@arm.com * 1718922Swilliam.wang@arm.com * @return a reference to the port with the given name 1728850Sandreas.hansson@arm.com */ 1739294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1749294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1758850Sandreas.hansson@arm.com 1769332Sdam.sunwoo@arm.com /** Get cpu task id */ 1779332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1789332Sdam.sunwoo@arm.com /** Set cpu task id */ 1799332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1809332Sdam.sunwoo@arm.com 1819332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 1829332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 1839332Sdam.sunwoo@arm.com 1847914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1857914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1863814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1873814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1881634SN/A 1895664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1905664Sgblack@eecs.umich.edu 1912SN/A protected: 1925704Snate@binkert.org TheISA::Interrupts *interrupts; 1932SN/A 1942SN/A public: 1955645Sgblack@eecs.umich.edu TheISA::Interrupts * 1965645Sgblack@eecs.umich.edu getInterruptController() 1975645Sgblack@eecs.umich.edu { 1985647Sgblack@eecs.umich.edu return interrupts; 1995645Sgblack@eecs.umich.edu } 2005645Sgblack@eecs.umich.edu 2015807Snate@binkert.org virtual void wakeup() = 0; 2025807Snate@binkert.org 2035807Snate@binkert.org void 2045807Snate@binkert.org postInterrupt(int int_num, int index) 2055807Snate@binkert.org { 2065807Snate@binkert.org interrupts->post(int_num, index); 2078779Sgblack@eecs.umich.edu if (FullSystem) 2088779Sgblack@eecs.umich.edu wakeup(); 2095807Snate@binkert.org } 2105807Snate@binkert.org 2115807Snate@binkert.org void 2125807Snate@binkert.org clearInterrupt(int int_num, int index) 2135807Snate@binkert.org { 2145807Snate@binkert.org interrupts->clear(int_num, index); 2155807Snate@binkert.org } 2165807Snate@binkert.org 2175807Snate@binkert.org void 2185807Snate@binkert.org clearInterrupts() 2195807Snate@binkert.org { 2205807Snate@binkert.org interrupts->clearAll(); 2215807Snate@binkert.org } 2222SN/A 2235704Snate@binkert.org bool 2245704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2255704Snate@binkert.org { 2268793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2275704Snate@binkert.org } 2281917SN/A 2291917SN/A class ProfileEvent : public Event 2301917SN/A { 2311917SN/A private: 2321917SN/A BaseCPU *cpu; 2335536Srstrong@hp.com Tick interval; 2341917SN/A 2351917SN/A public: 2365536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2371917SN/A void process(); 2381917SN/A }; 2391917SN/A ProfileEvent *profileEvent; 2402SN/A 2412SN/A protected: 2422680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2432SN/A 2444776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2454776Sgblack@eecs.umich.edu 2462SN/A public: 247393SN/A 2487764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2497764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2507764Sgblack@eecs.umich.edu 2514776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2524776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2534776Sgblack@eecs.umich.edu 254393SN/A /// Notify the CPU that the indicated context is now active. The 255393SN/A /// delay parameter indicates the number of ticks to wait before 256393SN/A /// executing (typically 0 or 1). 2579180Sandreas.hansson@arm.com virtual void activateContext(ThreadID thread_num, Cycles delay) {} 258393SN/A 259393SN/A /// Notify the CPU that the indicated context is now suspended. 2608737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 261393SN/A 262393SN/A /// Notify the CPU that the indicated context is now deallocated. 2638737Skoansin.tan@gmail.com virtual void deallocateContext(ThreadID thread_num) {} 264393SN/A 265393SN/A /// Notify the CPU that the indicated context is now halted. 2668737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2672SN/A 2684000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2694000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2704000Ssaidi@eecs.umich.edu 2714000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2729652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2734000Ssaidi@eecs.umich.edu 27410030SAli.Saidi@ARM.com /// Get the number of thread contexts available 27510030SAli.Saidi@ARM.com unsigned numContexts() { return threadContexts.size(); } 27610030SAli.Saidi@ARM.com 2772SN/A public: 2785529Snate@binkert.org typedef BaseCPUParams Params; 2795529Snate@binkert.org const Params *params() const 2805529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2818876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2821191SN/A virtual ~BaseCPU(); 2832SN/A 2841129SN/A virtual void init(); 2851917SN/A virtual void startup(); 2862SN/A virtual void regStats(); 2872SN/A 2886221Snate@binkert.org virtual void activateWhenReady(ThreadID tid) {}; 2892103SN/A 2902680Sktlim@umich.edu void registerThreadContexts(); 291180SN/A 2929254SAndreas.Sandberg@arm.com /** 2939254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 2949254SAndreas.Sandberg@arm.com * 2959254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 2969254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 2979254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 2989254SAndreas.Sandberg@arm.com */ 2992798Sktlim@umich.edu virtual void switchOut(); 300180SN/A 3019254SAndreas.Sandberg@arm.com /** 3029254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 3039254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3049254SAndreas.Sandberg@arm.com * 3059254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3069254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3079254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3089254SAndreas.Sandberg@arm.com * CPU. 3099254SAndreas.Sandberg@arm.com * 3109254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3119254SAndreas.Sandberg@arm.com */ 3129254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 313180SN/A 314124SN/A /** 3159446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3169446SAndreas.Sandberg@ARM.com * 3179446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3189446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3199446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3209446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3219446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3229446SAndreas.Sandberg@ARM.com */ 3239446SAndreas.Sandberg@ARM.com void flushTLBs(); 3249446SAndreas.Sandberg@ARM.com 3259446SAndreas.Sandberg@ARM.com /** 3269430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3279430SAndreas.Sandberg@ARM.com * 3289430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3299430SAndreas.Sandberg@ARM.com */ 3309430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3319430SAndreas.Sandberg@ARM.com 3329430SAndreas.Sandberg@ARM.com /** 3339523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3349523SAndreas.Sandberg@ARM.com * CPU. 3359523SAndreas.Sandberg@ARM.com * 3369523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3379523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3389523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3399523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3409523SAndreas.Sandberg@ARM.com */ 3419523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3429523SAndreas.Sandberg@ARM.com 3439523SAndreas.Sandberg@ARM.com /** 344124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 345124SN/A * This is a constant for the duration of the simulation. 346124SN/A */ 3476221Snate@binkert.org ThreadID numThreads; 3482SN/A 349124SN/A /** 350124SN/A * Vector of per-thread instruction-based event queues. Used for 351124SN/A * scheduling events based on number of instructions committed by 352124SN/A * a particular thread. 353124SN/A */ 354503SN/A EventQueue **comInstEventQueue; 3552SN/A 356124SN/A /** 357124SN/A * Vector of per-thread load-based event queues. Used for 358124SN/A * scheduling events based on number of loads committed by 359124SN/A *a particular thread. 360124SN/A */ 361124SN/A EventQueue **comLoadEventQueue; 362124SN/A 3632SN/A System *system; 364921SN/A 365921SN/A /** 3669814Sandreas.hansson@arm.com * Get the cache line size of the system. 3679814Sandreas.hansson@arm.com */ 3689814Sandreas.hansson@arm.com inline unsigned int cacheLineSize() const { return _cacheLineSize; } 3699814Sandreas.hansson@arm.com 3709814Sandreas.hansson@arm.com /** 371921SN/A * Serialize this object to the given output stream. 3729448SAndreas.Sandberg@ARM.com * 3739448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 3749448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 3759448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 3769448SAndreas.Sandberg@ARM.com * reuse. 3779448SAndreas.Sandberg@ARM.com * 378921SN/A * @param os The stream to serialize to. 379921SN/A */ 380921SN/A virtual void serialize(std::ostream &os); 381921SN/A 382921SN/A /** 383921SN/A * Reconstruct the state of this object from a checkpoint. 3849448SAndreas.Sandberg@ARM.com * 3859448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 3869448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 3879448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 3889448SAndreas.Sandberg@ARM.com * promotes better code reuse. 3899448SAndreas.Sandberg@ARM.com 390921SN/A * @param cp The checkpoint use. 3919448SAndreas.Sandberg@ARM.com * @param section The section name of this object. 392921SN/A */ 393921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 394921SN/A 395124SN/A /** 3969448SAndreas.Sandberg@ARM.com * Serialize a single thread. 3979448SAndreas.Sandberg@ARM.com * 3989448SAndreas.Sandberg@ARM.com * @param os The stream to serialize to. 3999448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4009448SAndreas.Sandberg@ARM.com */ 4019448SAndreas.Sandberg@ARM.com virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 4029448SAndreas.Sandberg@ARM.com 4039448SAndreas.Sandberg@ARM.com /** 4049448SAndreas.Sandberg@ARM.com * Unserialize one thread. 4059448SAndreas.Sandberg@ARM.com * 4069448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 4079448SAndreas.Sandberg@ARM.com * @param section The section name of this thread. 4089448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4099448SAndreas.Sandberg@ARM.com */ 4109448SAndreas.Sandberg@ARM.com virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 4119448SAndreas.Sandberg@ARM.com ThreadID tid) {}; 4129448SAndreas.Sandberg@ARM.com 4138834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 4148834Satgutier@umich.edu 4158834Satgutier@umich.edu virtual Counter totalOps() const = 0; 416707SN/A 4179749Sandreas@sandberg.pp.se /** 4189749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4199749Sandreas@sandberg.pp.se * predefined number of instructions. 4209749Sandreas@sandberg.pp.se * 4219749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4229749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4239749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4249749Sandreas@sandberg.pp.se * instructions rather than ticks. 4259749Sandreas@sandberg.pp.se * 4269749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4279749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4289749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4299749Sandreas@sandberg.pp.se */ 4309749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4319749Sandreas@sandberg.pp.se 4329749Sandreas@sandberg.pp.se /** 4339749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4349749Sandreas@sandberg.pp.se * predefined number of load operations. 4359749Sandreas@sandberg.pp.se * 4369749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4379749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4389749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4399749Sandreas@sandberg.pp.se * loads rather than ticks. 4409749Sandreas@sandberg.pp.se * 4419749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4429749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4439749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4449749Sandreas@sandberg.pp.se */ 4459749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4469749Sandreas@sandberg.pp.se 4471191SN/A // Function tracing 4481191SN/A private: 4491191SN/A bool functionTracingEnabled; 4501191SN/A std::ostream *functionTraceStream; 4511191SN/A Addr currentFunctionStart; 4521191SN/A Addr currentFunctionEnd; 4531191SN/A Tick functionEntryTick; 4541191SN/A void enableFunctionTrace(); 4551191SN/A void traceFunctionsInternal(Addr pc); 4561191SN/A 4578662SAli.Saidi@ARM.com private: 4588662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 4598662SAli.Saidi@ARM.com 4608662SAli.Saidi@ARM.com public: 4611191SN/A void traceFunctions(Addr pc) 4621191SN/A { 4631191SN/A if (functionTracingEnabled) 4641191SN/A traceFunctionsInternal(pc); 4651191SN/A } 4661191SN/A 4672SN/A static int numSimulatedCPUs() { return cpuList.size(); } 4688834Satgutier@umich.edu static Counter numSimulatedInsts() 469707SN/A { 470707SN/A Counter total = 0; 471707SN/A 472707SN/A int size = cpuList.size(); 473707SN/A for (int i = 0; i < size; ++i) 4748834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 4758834Satgutier@umich.edu 4768834Satgutier@umich.edu return total; 4778834Satgutier@umich.edu } 4788834Satgutier@umich.edu 4798834Satgutier@umich.edu static Counter numSimulatedOps() 4808834Satgutier@umich.edu { 4818834Satgutier@umich.edu Counter total = 0; 4828834Satgutier@umich.edu 4838834Satgutier@umich.edu int size = cpuList.size(); 4848834Satgutier@umich.edu for (int i = 0; i < size; ++i) 4858834Satgutier@umich.edu total += cpuList[i]->totalOps(); 486707SN/A 487707SN/A return total; 488707SN/A } 489707SN/A 490707SN/A public: 491707SN/A // Number of CPU cycles simulated 4925999Snate@binkert.org Stats::Scalar numCycles; 4937914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 4947914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 4952SN/A}; 4962SN/A 4979850Sandreas.hansson@arm.com#endif // THE_ISA == NULL_ISA 4989850Sandreas.hansson@arm.com 4991717SN/A#endif // __CPU_BASE_HH__ 500