base.cc revision 8922
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "cpu/base.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/sim_events.hh" 66#include "sim/sim_exit.hh" 67#include "sim/system.hh" 68 69// Hack 70#include "sim/stat_control.hh" 71 72using namespace std; 73 74vector<BaseCPU *> BaseCPU::cpuList; 75 76// This variable reflects the max number of threads in any CPU. Be 77// careful to only use it once all the CPUs that you care about have 78// been initialized 79int maxThreadsPerCPU = 1; 80 81CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 82 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 83 cpu(_cpu), _repeatEvent(true) 84{ 85 if (_interval) 86 cpu->schedule(this, curTick() + _interval); 87} 88 89void 90CPUProgressEvent::process() 91{ 92 Counter temp = cpu->totalOps(); 93#ifndef NDEBUG 94 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 95 96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 97 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 98 ipc); 99 ipc = 0.0; 100#else 101 cprintf("%lli: %s progress event, total committed:%i, progress insts " 102 "committed: %lli\n", curTick(), cpu->name(), temp, 103 temp - lastNumInst); 104#endif 105 lastNumInst = temp; 106 107 if (_repeatEvent) 108 cpu->schedule(this, curTick() + _interval); 109} 110 111const char * 112CPUProgressEvent::description() const 113{ 114 return "CPU Progress"; 115} 116 117BaseCPU::BaseCPU(Params *p, bool is_checker) 118 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 119 _instMasterId(p->system->getMasterId(name() + ".inst")), 120 _dataMasterId(p->system->getMasterId(name() + ".data")), 121 interrupts(p->interrupts), 122 numThreads(p->numThreads), system(p->system), 123 phase(p->phase) 124{ 125// currentTick = curTick(); 126 127 // if Python did not provide a valid ID, do it here 128 if (_cpuId == -1 ) { 129 _cpuId = cpuList.size(); 130 } 131 132 // add self to global list of CPUs 133 cpuList.push_back(this); 134 135 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 136 137 if (numThreads > maxThreadsPerCPU) 138 maxThreadsPerCPU = numThreads; 139 140 // allocate per-thread instruction-based event queues 141 comInstEventQueue = new EventQueue *[numThreads]; 142 for (ThreadID tid = 0; tid < numThreads; ++tid) 143 comInstEventQueue[tid] = 144 new EventQueue("instruction-based event queue"); 145 146 // 147 // set up instruction-count-based termination events, if any 148 // 149 if (p->max_insts_any_thread != 0) { 150 const char *cause = "a thread reached the max instruction count"; 151 for (ThreadID tid = 0; tid < numThreads; ++tid) { 152 Event *event = new SimLoopExitEvent(cause, 0); 153 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 154 } 155 } 156 157 if (p->max_insts_all_threads != 0) { 158 const char *cause = "all threads reached the max instruction count"; 159 160 // allocate & initialize shared downcounter: each event will 161 // decrement this when triggered; simulation will terminate 162 // when counter reaches 0 163 int *counter = new int; 164 *counter = numThreads; 165 for (ThreadID tid = 0; tid < numThreads; ++tid) { 166 Event *event = new CountedExitEvent(cause, *counter); 167 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 168 } 169 } 170 171 // allocate per-thread load-based event queues 172 comLoadEventQueue = new EventQueue *[numThreads]; 173 for (ThreadID tid = 0; tid < numThreads; ++tid) 174 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 175 176 // 177 // set up instruction-count-based termination events, if any 178 // 179 if (p->max_loads_any_thread != 0) { 180 const char *cause = "a thread reached the max load count"; 181 for (ThreadID tid = 0; tid < numThreads; ++tid) { 182 Event *event = new SimLoopExitEvent(cause, 0); 183 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 184 } 185 } 186 187 if (p->max_loads_all_threads != 0) { 188 const char *cause = "all threads reached the max load count"; 189 // allocate & initialize shared downcounter: each event will 190 // decrement this when triggered; simulation will terminate 191 // when counter reaches 0 192 int *counter = new int; 193 *counter = numThreads; 194 for (ThreadID tid = 0; tid < numThreads; ++tid) { 195 Event *event = new CountedExitEvent(cause, *counter); 196 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 197 } 198 } 199 200 functionTracingEnabled = false; 201 if (p->function_trace) { 202 const string fname = csprintf("ftrace.%s", name()); 203 functionTraceStream = simout.find(fname); 204 if (!functionTraceStream) 205 functionTraceStream = simout.create(fname); 206 207 currentFunctionStart = currentFunctionEnd = 0; 208 functionEntryTick = p->function_trace_start; 209 210 if (p->function_trace_start == 0) { 211 functionTracingEnabled = true; 212 } else { 213 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 214 Event *event = new wrap(this, true); 215 schedule(event, p->function_trace_start); 216 } 217 } 218 219 // The interrupts should always be present unless this CPU is 220 // switched in later or in case it is a checker CPU 221 if (!params()->defer_registration && !is_checker) { 222 if (interrupts) { 223 interrupts->setCPU(this); 224 } else { 225 fatal("CPU %s has no interrupt controller.\n" 226 "Ensure createInterruptController() is called.\n", name()); 227 } 228 } 229 230 if (FullSystem) { 231 profileEvent = NULL; 232 if (params()->profile) 233 profileEvent = new ProfileEvent(this, params()->profile); 234 } 235 tracer = params()->tracer; 236} 237 238void 239BaseCPU::enableFunctionTrace() 240{ 241 functionTracingEnabled = true; 242} 243 244BaseCPU::~BaseCPU() 245{ 246} 247 248void 249BaseCPU::init() 250{ 251 if (!params()->defer_registration) 252 registerThreadContexts(); 253} 254 255void 256BaseCPU::startup() 257{ 258 if (FullSystem) { 259 if (!params()->defer_registration && profileEvent) 260 schedule(profileEvent, curTick()); 261 } 262 263 if (params()->progress_interval) { 264 Tick num_ticks = ticks(params()->progress_interval); 265 266 new CPUProgressEvent(this, num_ticks); 267 } 268} 269 270 271void 272BaseCPU::regStats() 273{ 274 using namespace Stats; 275 276 numCycles 277 .name(name() + ".numCycles") 278 .desc("number of cpu cycles simulated") 279 ; 280 281 numWorkItemsStarted 282 .name(name() + ".numWorkItemsStarted") 283 .desc("number of work items this cpu started") 284 ; 285 286 numWorkItemsCompleted 287 .name(name() + ".numWorkItemsCompleted") 288 .desc("number of work items this cpu completed") 289 ; 290 291 int size = threadContexts.size(); 292 if (size > 1) { 293 for (int i = 0; i < size; ++i) { 294 stringstream namestr; 295 ccprintf(namestr, "%s.ctx%d", name(), i); 296 threadContexts[i]->regStats(namestr.str()); 297 } 298 } else if (size == 1) 299 threadContexts[0]->regStats(name()); 300} 301 302MasterPort & 303BaseCPU::getMasterPort(const string &if_name, int idx) 304{ 305 // Get the right port based on name. This applies to all the 306 // subclasses of the base CPU and relies on their implementation 307 // of getDataPort and getInstPort. In all cases there methods 308 // return a CpuPort pointer. 309 if (if_name == "dcache_port") 310 return getDataPort(); 311 else if (if_name == "icache_port") 312 return getInstPort(); 313 else 314 return MemObject::getMasterPort(if_name, idx); 315} 316 317Tick 318BaseCPU::nextCycle() 319{ 320 Tick next_tick = curTick() - phase + clock - 1; 321 next_tick -= (next_tick % clock); 322 next_tick += phase; 323 return next_tick; 324} 325 326Tick 327BaseCPU::nextCycle(Tick begin_tick) 328{ 329 Tick next_tick = begin_tick; 330 if (next_tick % clock != 0) 331 next_tick = next_tick - (next_tick % clock) + clock; 332 next_tick += phase; 333 334 assert(next_tick >= curTick()); 335 return next_tick; 336} 337 338void 339BaseCPU::registerThreadContexts() 340{ 341 ThreadID size = threadContexts.size(); 342 for (ThreadID tid = 0; tid < size; ++tid) { 343 ThreadContext *tc = threadContexts[tid]; 344 345 /** This is so that contextId and cpuId match where there is a 346 * 1cpu:1context relationship. Otherwise, the order of registration 347 * could affect the assignment and cpu 1 could have context id 3, for 348 * example. We may even want to do something like this for SMT so that 349 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 350 * I'll just do this for now 351 */ 352 if (numThreads == 1) 353 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 354 else 355 tc->setContextId(system->registerThreadContext(tc)); 356 357 if (!FullSystem) 358 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 359 } 360} 361 362 363int 364BaseCPU::findContext(ThreadContext *tc) 365{ 366 ThreadID size = threadContexts.size(); 367 for (ThreadID tid = 0; tid < size; ++tid) { 368 if (tc == threadContexts[tid]) 369 return tid; 370 } 371 return 0; 372} 373 374void 375BaseCPU::switchOut() 376{ 377 if (profileEvent && profileEvent->scheduled()) 378 deschedule(profileEvent); 379} 380 381void 382BaseCPU::takeOverFrom(BaseCPU *oldCPU) 383{ 384 assert(threadContexts.size() == oldCPU->threadContexts.size()); 385 386 _cpuId = oldCPU->cpuId(); 387 388 ThreadID size = threadContexts.size(); 389 for (ThreadID i = 0; i < size; ++i) { 390 ThreadContext *newTC = threadContexts[i]; 391 ThreadContext *oldTC = oldCPU->threadContexts[i]; 392 393 newTC->takeOverFrom(oldTC); 394 395 CpuEvent::replaceThreadContext(oldTC, newTC); 396 397 assert(newTC->contextId() == oldTC->contextId()); 398 assert(newTC->threadId() == oldTC->threadId()); 399 system->replaceThreadContext(newTC, newTC->contextId()); 400 401 /* This code no longer works since the zero register (e.g., 402 * r31 on Alpha) doesn't necessarily contain zero at this 403 * point. 404 if (DTRACE(Context)) 405 ThreadContext::compare(oldTC, newTC); 406 */ 407 408 MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 409 MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 410 MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 411 MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 412 413 // Move over any table walker ports if they exist 414 if (new_itb_port && !new_itb_port->isConnected()) { 415 assert(old_itb_port); 416 SlavePort &slavePort = old_itb_port->getSlavePort(); 417 new_itb_port->bind(slavePort); 418 } 419 if (new_dtb_port && !new_dtb_port->isConnected()) { 420 assert(old_dtb_port); 421 SlavePort &slavePort = old_dtb_port->getSlavePort(); 422 new_dtb_port->bind(slavePort); 423 } 424 425 // Checker whether or not we have to transfer CheckerCPU 426 // objects over in the switch 427 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 428 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 429 if (oldChecker && newChecker) { 430 MasterPort *old_checker_itb_port = 431 oldChecker->getITBPtr()->getMasterPort(); 432 MasterPort *old_checker_dtb_port = 433 oldChecker->getDTBPtr()->getMasterPort(); 434 MasterPort *new_checker_itb_port = 435 newChecker->getITBPtr()->getMasterPort(); 436 MasterPort *new_checker_dtb_port = 437 newChecker->getDTBPtr()->getMasterPort(); 438 439 // Move over any table walker ports if they exist for checker 440 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 441 assert(old_checker_itb_port); 442 SlavePort &slavePort = old_checker_itb_port->getSlavePort();; 443 new_checker_itb_port->bind(slavePort); 444 } 445 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 446 assert(old_checker_dtb_port); 447 SlavePort &slavePort = old_checker_dtb_port->getSlavePort();; 448 new_checker_dtb_port->bind(slavePort); 449 } 450 } 451 } 452 453 interrupts = oldCPU->interrupts; 454 interrupts->setCPU(this); 455 456 if (FullSystem) { 457 for (ThreadID i = 0; i < size; ++i) 458 threadContexts[i]->profileClear(); 459 460 if (profileEvent) 461 schedule(profileEvent, curTick()); 462 } 463 464 // Connect new CPU to old CPU's memory only if new CPU isn't 465 // connected to anything. Also connect old CPU's memory to new 466 // CPU. 467 if (!getInstPort().isConnected()) { 468 getInstPort().bind(oldCPU->getInstPort().getSlavePort()); 469 } 470 471 if (!getDataPort().isConnected()) { 472 getDataPort().bind(oldCPU->getDataPort().getSlavePort()); 473 } 474} 475 476 477BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 478 : cpu(_cpu), interval(_interval) 479{ } 480 481void 482BaseCPU::ProfileEvent::process() 483{ 484 ThreadID size = cpu->threadContexts.size(); 485 for (ThreadID i = 0; i < size; ++i) { 486 ThreadContext *tc = cpu->threadContexts[i]; 487 tc->profileSample(); 488 } 489 490 cpu->schedule(this, curTick() + interval); 491} 492 493void 494BaseCPU::serialize(std::ostream &os) 495{ 496 SERIALIZE_SCALAR(instCnt); 497 interrupts->serialize(os); 498} 499 500void 501BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 502{ 503 UNSERIALIZE_SCALAR(instCnt); 504 interrupts->unserialize(cp, section); 505} 506 507void 508BaseCPU::traceFunctionsInternal(Addr pc) 509{ 510 if (!debugSymbolTable) 511 return; 512 513 // if pc enters different function, print new function symbol and 514 // update saved range. Otherwise do nothing. 515 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 516 string sym_str; 517 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 518 currentFunctionStart, 519 currentFunctionEnd); 520 521 if (!found) { 522 // no symbol found: use addr as label 523 sym_str = csprintf("0x%x", pc); 524 currentFunctionStart = pc; 525 currentFunctionEnd = pc + 1; 526 } 527 528 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 529 curTick() - functionEntryTick, curTick(), sym_str); 530 functionEntryTick = curTick(); 531 } 532} 533 534bool 535BaseCPU::CpuPort::recvTiming(PacketPtr pkt) 536{ 537 panic("BaseCPU doesn't expect recvTiming callback!"); 538 return true; 539} 540 541void 542BaseCPU::CpuPort::recvRetry() 543{ 544 panic("BaseCPU doesn't expect recvRetry callback!"); 545} 546 547Tick 548BaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 549{ 550 panic("BaseCPU doesn't expect recvAtomic callback!"); 551 return curTick(); 552} 553 554void 555BaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 556{ 557 // No internal storage to update (in the general case). In the 558 // long term this should never be called, but that assumed a split 559 // into master/slave and request/response. 560} 561