base.cc revision 8834
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "config/use_checker.hh" 57#include "cpu/base.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/sim_events.hh" 66#include "sim/sim_exit.hh" 67#include "sim/system.hh" 68 69#if USE_CHECKER 70#include "cpu/checker/cpu.hh" 71#endif 72 73// Hack 74#include "sim/stat_control.hh" 75 76using namespace std; 77 78vector<BaseCPU *> BaseCPU::cpuList; 79 80// This variable reflects the max number of threads in any CPU. Be 81// careful to only use it once all the CPUs that you care about have 82// been initialized 83int maxThreadsPerCPU = 1; 84 85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 86 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 87 cpu(_cpu), _repeatEvent(true) 88{ 89 if (_interval) 90 cpu->schedule(this, curTick() + _interval); 91} 92 93void 94CPUProgressEvent::process() 95{ 96 Counter temp = cpu->totalOps(); 97#ifndef NDEBUG 98 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 99 100 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 101 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 102 ipc); 103 ipc = 0.0; 104#else 105 cprintf("%lli: %s progress event, total committed:%i, progress insts " 106 "committed: %lli\n", curTick(), cpu->name(), temp, 107 temp - lastNumInst); 108#endif 109 lastNumInst = temp; 110 111 if (_repeatEvent) 112 cpu->schedule(this, curTick() + _interval); 113} 114 115const char * 116CPUProgressEvent::description() const 117{ 118 return "CPU Progress"; 119} 120 121BaseCPU::BaseCPU(Params *p) 122 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 123 _instMasterId(p->system->getMasterId(name() + ".inst")), 124 _dataMasterId(p->system->getMasterId(name() + ".data")), 125 interrupts(p->interrupts), 126 numThreads(p->numThreads), system(p->system), 127 phase(p->phase) 128{ 129// currentTick = curTick(); 130 131 // if Python did not provide a valid ID, do it here 132 if (_cpuId == -1 ) { 133 _cpuId = cpuList.size(); 134 } 135 136 // add self to global list of CPUs 137 cpuList.push_back(this); 138 139 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 140 141 if (numThreads > maxThreadsPerCPU) 142 maxThreadsPerCPU = numThreads; 143 144 // allocate per-thread instruction-based event queues 145 comInstEventQueue = new EventQueue *[numThreads]; 146 for (ThreadID tid = 0; tid < numThreads; ++tid) 147 comInstEventQueue[tid] = 148 new EventQueue("instruction-based event queue"); 149 150 // 151 // set up instruction-count-based termination events, if any 152 // 153 if (p->max_insts_any_thread != 0) { 154 const char *cause = "a thread reached the max instruction count"; 155 for (ThreadID tid = 0; tid < numThreads; ++tid) { 156 Event *event = new SimLoopExitEvent(cause, 0); 157 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 158 } 159 } 160 161 if (p->max_insts_all_threads != 0) { 162 const char *cause = "all threads reached the max instruction count"; 163 164 // allocate & initialize shared downcounter: each event will 165 // decrement this when triggered; simulation will terminate 166 // when counter reaches 0 167 int *counter = new int; 168 *counter = numThreads; 169 for (ThreadID tid = 0; tid < numThreads; ++tid) { 170 Event *event = new CountedExitEvent(cause, *counter); 171 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 172 } 173 } 174 175 // allocate per-thread load-based event queues 176 comLoadEventQueue = new EventQueue *[numThreads]; 177 for (ThreadID tid = 0; tid < numThreads; ++tid) 178 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 179 180 // 181 // set up instruction-count-based termination events, if any 182 // 183 if (p->max_loads_any_thread != 0) { 184 const char *cause = "a thread reached the max load count"; 185 for (ThreadID tid = 0; tid < numThreads; ++tid) { 186 Event *event = new SimLoopExitEvent(cause, 0); 187 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 188 } 189 } 190 191 if (p->max_loads_all_threads != 0) { 192 const char *cause = "all threads reached the max load count"; 193 // allocate & initialize shared downcounter: each event will 194 // decrement this when triggered; simulation will terminate 195 // when counter reaches 0 196 int *counter = new int; 197 *counter = numThreads; 198 for (ThreadID tid = 0; tid < numThreads; ++tid) { 199 Event *event = new CountedExitEvent(cause, *counter); 200 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 201 } 202 } 203 204 functionTracingEnabled = false; 205 if (p->function_trace) { 206 const string fname = csprintf("ftrace.%s", name()); 207 functionTraceStream = simout.find(fname); 208 if (!functionTraceStream) 209 functionTraceStream = simout.create(fname); 210 211 currentFunctionStart = currentFunctionEnd = 0; 212 functionEntryTick = p->function_trace_start; 213 214 if (p->function_trace_start == 0) { 215 functionTracingEnabled = true; 216 } else { 217 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 218 Event *event = new wrap(this, true); 219 schedule(event, p->function_trace_start); 220 } 221 } 222 // Check if CPU model has interrupts connected. The CheckerCPU 223 // cannot take interrupts directly for example. 224 if (interrupts) 225 interrupts->setCPU(this); 226 227 if (FullSystem) { 228 profileEvent = NULL; 229 if (params()->profile) 230 profileEvent = new ProfileEvent(this, params()->profile); 231 } 232 tracer = params()->tracer; 233} 234 235void 236BaseCPU::enableFunctionTrace() 237{ 238 functionTracingEnabled = true; 239} 240 241BaseCPU::~BaseCPU() 242{ 243} 244 245void 246BaseCPU::init() 247{ 248 if (!params()->defer_registration) 249 registerThreadContexts(); 250} 251 252void 253BaseCPU::startup() 254{ 255 if (FullSystem) { 256 if (!params()->defer_registration && profileEvent) 257 schedule(profileEvent, curTick()); 258 } 259 260 if (params()->progress_interval) { 261 Tick num_ticks = ticks(params()->progress_interval); 262 263 new CPUProgressEvent(this, num_ticks); 264 } 265} 266 267 268void 269BaseCPU::regStats() 270{ 271 using namespace Stats; 272 273 numCycles 274 .name(name() + ".numCycles") 275 .desc("number of cpu cycles simulated") 276 ; 277 278 numWorkItemsStarted 279 .name(name() + ".numWorkItemsStarted") 280 .desc("number of work items this cpu started") 281 ; 282 283 numWorkItemsCompleted 284 .name(name() + ".numWorkItemsCompleted") 285 .desc("number of work items this cpu completed") 286 ; 287 288 int size = threadContexts.size(); 289 if (size > 1) { 290 for (int i = 0; i < size; ++i) { 291 stringstream namestr; 292 ccprintf(namestr, "%s.ctx%d", name(), i); 293 threadContexts[i]->regStats(namestr.str()); 294 } 295 } else if (size == 1) 296 threadContexts[0]->regStats(name()); 297} 298 299Tick 300BaseCPU::nextCycle() 301{ 302 Tick next_tick = curTick() - phase + clock - 1; 303 next_tick -= (next_tick % clock); 304 next_tick += phase; 305 return next_tick; 306} 307 308Tick 309BaseCPU::nextCycle(Tick begin_tick) 310{ 311 Tick next_tick = begin_tick; 312 if (next_tick % clock != 0) 313 next_tick = next_tick - (next_tick % clock) + clock; 314 next_tick += phase; 315 316 assert(next_tick >= curTick()); 317 return next_tick; 318} 319 320void 321BaseCPU::registerThreadContexts() 322{ 323 ThreadID size = threadContexts.size(); 324 for (ThreadID tid = 0; tid < size; ++tid) { 325 ThreadContext *tc = threadContexts[tid]; 326 327 /** This is so that contextId and cpuId match where there is a 328 * 1cpu:1context relationship. Otherwise, the order of registration 329 * could affect the assignment and cpu 1 could have context id 3, for 330 * example. We may even want to do something like this for SMT so that 331 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 332 * I'll just do this for now 333 */ 334 if (numThreads == 1) 335 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 336 else 337 tc->setContextId(system->registerThreadContext(tc)); 338 339 if (!FullSystem) 340 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 341 } 342} 343 344 345int 346BaseCPU::findContext(ThreadContext *tc) 347{ 348 ThreadID size = threadContexts.size(); 349 for (ThreadID tid = 0; tid < size; ++tid) { 350 if (tc == threadContexts[tid]) 351 return tid; 352 } 353 return 0; 354} 355 356void 357BaseCPU::switchOut() 358{ 359 if (profileEvent && profileEvent->scheduled()) 360 deschedule(profileEvent); 361} 362 363void 364BaseCPU::takeOverFrom(BaseCPU *oldCPU) 365{ 366 Port *ic = getPort("icache_port"); 367 Port *dc = getPort("dcache_port"); 368 assert(threadContexts.size() == oldCPU->threadContexts.size()); 369 370 _cpuId = oldCPU->cpuId(); 371 372 ThreadID size = threadContexts.size(); 373 for (ThreadID i = 0; i < size; ++i) { 374 ThreadContext *newTC = threadContexts[i]; 375 ThreadContext *oldTC = oldCPU->threadContexts[i]; 376 377 newTC->takeOverFrom(oldTC); 378 379 CpuEvent::replaceThreadContext(oldTC, newTC); 380 381 assert(newTC->contextId() == oldTC->contextId()); 382 assert(newTC->threadId() == oldTC->threadId()); 383 system->replaceThreadContext(newTC, newTC->contextId()); 384 385 /* This code no longer works since the zero register (e.g., 386 * r31 on Alpha) doesn't necessarily contain zero at this 387 * point. 388 if (DTRACE(Context)) 389 ThreadContext::compare(oldTC, newTC); 390 */ 391 392 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 393 old_itb_port = oldTC->getITBPtr()->getPort(); 394 old_dtb_port = oldTC->getDTBPtr()->getPort(); 395 new_itb_port = newTC->getITBPtr()->getPort(); 396 new_dtb_port = newTC->getDTBPtr()->getPort(); 397 398 // Move over any table walker ports if they exist 399 if (new_itb_port && !new_itb_port->isConnected()) { 400 assert(old_itb_port); 401 Port *peer = old_itb_port->getPeer();; 402 new_itb_port->setPeer(peer); 403 peer->setPeer(new_itb_port); 404 } 405 if (new_dtb_port && !new_dtb_port->isConnected()) { 406 assert(old_dtb_port); 407 Port *peer = old_dtb_port->getPeer();; 408 new_dtb_port->setPeer(peer); 409 peer->setPeer(new_dtb_port); 410 } 411 412#if USE_CHECKER 413 Port *old_checker_itb_port, *old_checker_dtb_port; 414 Port *new_checker_itb_port, *new_checker_dtb_port; 415 416 CheckerCPU *oldChecker = 417 dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr()); 418 CheckerCPU *newChecker = 419 dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr()); 420 old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 421 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 422 new_checker_itb_port = newChecker->getITBPtr()->getPort(); 423 new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 424 425 // Move over any table walker ports if they exist for checker 426 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 427 assert(old_checker_itb_port); 428 Port *peer = old_checker_itb_port->getPeer();; 429 new_checker_itb_port->setPeer(peer); 430 peer->setPeer(new_checker_itb_port); 431 } 432 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 433 assert(old_checker_dtb_port); 434 Port *peer = old_checker_dtb_port->getPeer();; 435 new_checker_dtb_port->setPeer(peer); 436 peer->setPeer(new_checker_dtb_port); 437 } 438#endif 439 440 } 441 442 interrupts = oldCPU->interrupts; 443 interrupts->setCPU(this); 444 445 if (FullSystem) { 446 for (ThreadID i = 0; i < size; ++i) 447 threadContexts[i]->profileClear(); 448 449 if (profileEvent) 450 schedule(profileEvent, curTick()); 451 } 452 453 // Connect new CPU to old CPU's memory only if new CPU isn't 454 // connected to anything. Also connect old CPU's memory to new 455 // CPU. 456 if (!ic->isConnected()) { 457 Port *peer = oldCPU->getPort("icache_port")->getPeer(); 458 ic->setPeer(peer); 459 peer->setPeer(ic); 460 } 461 462 if (!dc->isConnected()) { 463 Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 464 dc->setPeer(peer); 465 peer->setPeer(dc); 466 } 467} 468 469 470BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 471 : cpu(_cpu), interval(_interval) 472{ } 473 474void 475BaseCPU::ProfileEvent::process() 476{ 477 ThreadID size = cpu->threadContexts.size(); 478 for (ThreadID i = 0; i < size; ++i) { 479 ThreadContext *tc = cpu->threadContexts[i]; 480 tc->profileSample(); 481 } 482 483 cpu->schedule(this, curTick() + interval); 484} 485 486void 487BaseCPU::serialize(std::ostream &os) 488{ 489 SERIALIZE_SCALAR(instCnt); 490 interrupts->serialize(os); 491} 492 493void 494BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 495{ 496 UNSERIALIZE_SCALAR(instCnt); 497 interrupts->unserialize(cp, section); 498} 499 500void 501BaseCPU::traceFunctionsInternal(Addr pc) 502{ 503 if (!debugSymbolTable) 504 return; 505 506 // if pc enters different function, print new function symbol and 507 // update saved range. Otherwise do nothing. 508 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 509 string sym_str; 510 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 511 currentFunctionStart, 512 currentFunctionEnd); 513 514 if (!found) { 515 // no symbol found: use addr as label 516 sym_str = csprintf("0x%x", pc); 517 currentFunctionStart = pc; 518 currentFunctionEnd = pc + 1; 519 } 520 521 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 522 curTick() - functionEntryTick, curTick(), sym_str); 523 functionEntryTick = curTick(); 524 } 525} 526 527bool 528BaseCPU::CpuPort::recvTiming(PacketPtr pkt) 529{ 530 panic("BaseCPU doesn't expect recvTiming callback!"); 531 return true; 532} 533 534void 535BaseCPU::CpuPort::recvRetry() 536{ 537 panic("BaseCPU doesn't expect recvRetry callback!"); 538} 539 540Tick 541BaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 542{ 543 panic("BaseCPU doesn't expect recvAtomic callback!"); 544 return curTick(); 545} 546 547void 548BaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 549{ 550 // No internal storage to update (in the general case). In the 551 // long term this should never be called, but that assumed a split 552 // into master/slave and request/response. 553} 554 555void 556BaseCPU::CpuPort::recvRangeChange() 557{ 558} 559