base.cc revision 8799:dac1e33e07b0 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 *          Nathan Binkert
43 *          Rick Strong
44 */
45
46#include <iostream>
47#include <sstream>
48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
56#include "cpu/base.hh"
57#include "cpu/cpuevent.hh"
58#include "cpu/profile.hh"
59#include "cpu/thread_context.hh"
60#include "debug/SyscallVerbose.hh"
61#include "params/BaseCPU.hh"
62#include "sim/full_system.hh"
63#include "sim/process.hh"
64#include "sim/sim_events.hh"
65#include "sim/sim_exit.hh"
66#include "sim/system.hh"
67
68// Hack
69#include "sim/stat_control.hh"
70
71using namespace std;
72
73vector<BaseCPU *> BaseCPU::cpuList;
74
75// This variable reflects the max number of threads in any CPU.  Be
76// careful to only use it once all the CPUs that you care about have
77// been initialized
78int maxThreadsPerCPU = 1;
79
80CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
81    : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
82      cpu(_cpu), _repeatEvent(true)
83{
84    if (_interval)
85        cpu->schedule(this, curTick() + _interval);
86}
87
88void
89CPUProgressEvent::process()
90{
91    Counter temp = cpu->totalInstructions();
92#ifndef NDEBUG
93    double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
94
95    DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
96             "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
97             ipc);
98    ipc = 0.0;
99#else
100    cprintf("%lli: %s progress event, total committed:%i, progress insts "
101            "committed: %lli\n", curTick(), cpu->name(), temp,
102            temp - lastNumInst);
103#endif
104    lastNumInst = temp;
105
106    if (_repeatEvent)
107        cpu->schedule(this, curTick() + _interval);
108}
109
110const char *
111CPUProgressEvent::description() const
112{
113    return "CPU Progress";
114}
115
116BaseCPU::BaseCPU(Params *p)
117    : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
118      interrupts(p->interrupts),
119      numThreads(p->numThreads), system(p->system),
120      phase(p->phase)
121{
122//    currentTick = curTick();
123
124    // if Python did not provide a valid ID, do it here
125    if (_cpuId == -1 ) {
126        _cpuId = cpuList.size();
127    }
128
129    // add self to global list of CPUs
130    cpuList.push_back(this);
131
132    DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
133
134    if (numThreads > maxThreadsPerCPU)
135        maxThreadsPerCPU = numThreads;
136
137    // allocate per-thread instruction-based event queues
138    comInstEventQueue = new EventQueue *[numThreads];
139    for (ThreadID tid = 0; tid < numThreads; ++tid)
140        comInstEventQueue[tid] =
141            new EventQueue("instruction-based event queue");
142
143    //
144    // set up instruction-count-based termination events, if any
145    //
146    if (p->max_insts_any_thread != 0) {
147        const char *cause = "a thread reached the max instruction count";
148        for (ThreadID tid = 0; tid < numThreads; ++tid) {
149            Event *event = new SimLoopExitEvent(cause, 0);
150            comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
151        }
152    }
153
154    if (p->max_insts_all_threads != 0) {
155        const char *cause = "all threads reached the max instruction count";
156
157        // allocate & initialize shared downcounter: each event will
158        // decrement this when triggered; simulation will terminate
159        // when counter reaches 0
160        int *counter = new int;
161        *counter = numThreads;
162        for (ThreadID tid = 0; tid < numThreads; ++tid) {
163            Event *event = new CountedExitEvent(cause, *counter);
164            comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
165        }
166    }
167
168    // allocate per-thread load-based event queues
169    comLoadEventQueue = new EventQueue *[numThreads];
170    for (ThreadID tid = 0; tid < numThreads; ++tid)
171        comLoadEventQueue[tid] = new EventQueue("load-based event queue");
172
173    //
174    // set up instruction-count-based termination events, if any
175    //
176    if (p->max_loads_any_thread != 0) {
177        const char *cause = "a thread reached the max load count";
178        for (ThreadID tid = 0; tid < numThreads; ++tid) {
179            Event *event = new SimLoopExitEvent(cause, 0);
180            comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
181        }
182    }
183
184    if (p->max_loads_all_threads != 0) {
185        const char *cause = "all threads reached the max load count";
186        // allocate & initialize shared downcounter: each event will
187        // decrement this when triggered; simulation will terminate
188        // when counter reaches 0
189        int *counter = new int;
190        *counter = numThreads;
191        for (ThreadID tid = 0; tid < numThreads; ++tid) {
192            Event *event = new CountedExitEvent(cause, *counter);
193            comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
194        }
195    }
196
197    functionTracingEnabled = false;
198    if (p->function_trace) {
199        const string fname = csprintf("ftrace.%s", name());
200        functionTraceStream = simout.find(fname);
201        if (!functionTraceStream)
202            functionTraceStream = simout.create(fname);
203
204        currentFunctionStart = currentFunctionEnd = 0;
205        functionEntryTick = p->function_trace_start;
206
207        if (p->function_trace_start == 0) {
208            functionTracingEnabled = true;
209        } else {
210            typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
211            Event *event = new wrap(this, true);
212            schedule(event, p->function_trace_start);
213        }
214    }
215    interrupts->setCPU(this);
216
217    if (FullSystem) {
218        profileEvent = NULL;
219        if (params()->profile)
220            profileEvent = new ProfileEvent(this, params()->profile);
221    }
222    tracer = params()->tracer;
223}
224
225void
226BaseCPU::enableFunctionTrace()
227{
228    functionTracingEnabled = true;
229}
230
231BaseCPU::~BaseCPU()
232{
233}
234
235void
236BaseCPU::init()
237{
238    if (!params()->defer_registration)
239        registerThreadContexts();
240}
241
242void
243BaseCPU::startup()
244{
245    if (FullSystem) {
246        if (!params()->defer_registration && profileEvent)
247            schedule(profileEvent, curTick());
248    }
249
250    if (params()->progress_interval) {
251        Tick num_ticks = ticks(params()->progress_interval);
252
253        new CPUProgressEvent(this, num_ticks);
254    }
255}
256
257
258void
259BaseCPU::regStats()
260{
261    using namespace Stats;
262
263    numCycles
264        .name(name() + ".numCycles")
265        .desc("number of cpu cycles simulated")
266        ;
267
268    numWorkItemsStarted
269        .name(name() + ".numWorkItemsStarted")
270        .desc("number of work items this cpu started")
271        ;
272
273    numWorkItemsCompleted
274        .name(name() + ".numWorkItemsCompleted")
275        .desc("number of work items this cpu completed")
276        ;
277
278    int size = threadContexts.size();
279    if (size > 1) {
280        for (int i = 0; i < size; ++i) {
281            stringstream namestr;
282            ccprintf(namestr, "%s.ctx%d", name(), i);
283            threadContexts[i]->regStats(namestr.str());
284        }
285    } else if (size == 1)
286        threadContexts[0]->regStats(name());
287}
288
289Tick
290BaseCPU::nextCycle()
291{
292    Tick next_tick = curTick() - phase + clock - 1;
293    next_tick -= (next_tick % clock);
294    next_tick += phase;
295    return next_tick;
296}
297
298Tick
299BaseCPU::nextCycle(Tick begin_tick)
300{
301    Tick next_tick = begin_tick;
302    if (next_tick % clock != 0)
303        next_tick = next_tick - (next_tick % clock) + clock;
304    next_tick += phase;
305
306    assert(next_tick >= curTick());
307    return next_tick;
308}
309
310void
311BaseCPU::registerThreadContexts()
312{
313    ThreadID size = threadContexts.size();
314    for (ThreadID tid = 0; tid < size; ++tid) {
315        ThreadContext *tc = threadContexts[tid];
316
317        /** This is so that contextId and cpuId match where there is a
318         * 1cpu:1context relationship.  Otherwise, the order of registration
319         * could affect the assignment and cpu 1 could have context id 3, for
320         * example.  We may even want to do something like this for SMT so that
321         * cpu 0 has the lowest thread contexts and cpu N has the highest, but
322         * I'll just do this for now
323         */
324        if (numThreads == 1)
325            tc->setContextId(system->registerThreadContext(tc, _cpuId));
326        else
327            tc->setContextId(system->registerThreadContext(tc));
328
329        if (!FullSystem)
330            tc->getProcessPtr()->assignThreadContext(tc->contextId());
331    }
332}
333
334
335int
336BaseCPU::findContext(ThreadContext *tc)
337{
338    ThreadID size = threadContexts.size();
339    for (ThreadID tid = 0; tid < size; ++tid) {
340        if (tc == threadContexts[tid])
341            return tid;
342    }
343    return 0;
344}
345
346void
347BaseCPU::switchOut()
348{
349    if (profileEvent && profileEvent->scheduled())
350        deschedule(profileEvent);
351}
352
353void
354BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
355{
356    assert(threadContexts.size() == oldCPU->threadContexts.size());
357
358    _cpuId = oldCPU->cpuId();
359
360    ThreadID size = threadContexts.size();
361    for (ThreadID i = 0; i < size; ++i) {
362        ThreadContext *newTC = threadContexts[i];
363        ThreadContext *oldTC = oldCPU->threadContexts[i];
364
365        newTC->takeOverFrom(oldTC);
366
367        CpuEvent::replaceThreadContext(oldTC, newTC);
368
369        assert(newTC->contextId() == oldTC->contextId());
370        assert(newTC->threadId() == oldTC->threadId());
371        system->replaceThreadContext(newTC, newTC->contextId());
372
373        /* This code no longer works since the zero register (e.g.,
374         * r31 on Alpha) doesn't necessarily contain zero at this
375         * point.
376           if (DTRACE(Context))
377            ThreadContext::compare(oldTC, newTC);
378        */
379
380        Port  *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
381        old_itb_port = oldTC->getITBPtr()->getPort();
382        old_dtb_port = oldTC->getDTBPtr()->getPort();
383        new_itb_port = newTC->getITBPtr()->getPort();
384        new_dtb_port = newTC->getDTBPtr()->getPort();
385
386        // Move over any table walker ports if they exist
387        if (new_itb_port && !new_itb_port->isConnected()) {
388            assert(old_itb_port);
389            Port *peer = old_itb_port->getPeer();;
390            new_itb_port->setPeer(peer);
391            peer->setPeer(new_itb_port);
392        }
393        if (new_dtb_port && !new_dtb_port->isConnected()) {
394            assert(old_dtb_port);
395            Port *peer = old_dtb_port->getPeer();;
396            new_dtb_port->setPeer(peer);
397            peer->setPeer(new_dtb_port);
398        }
399    }
400
401    interrupts = oldCPU->interrupts;
402    interrupts->setCPU(this);
403
404    if (FullSystem) {
405        for (ThreadID i = 0; i < size; ++i)
406            threadContexts[i]->profileClear();
407
408        if (profileEvent)
409            schedule(profileEvent, curTick());
410    }
411
412    // Connect new CPU to old CPU's memory only if new CPU isn't
413    // connected to anything.  Also connect old CPU's memory to new
414    // CPU.
415    if (!ic->isConnected()) {
416        Port *peer = oldCPU->getPort("icache_port")->getPeer();
417        ic->setPeer(peer);
418        peer->setPeer(ic);
419    }
420
421    if (!dc->isConnected()) {
422        Port *peer = oldCPU->getPort("dcache_port")->getPeer();
423        dc->setPeer(peer);
424        peer->setPeer(dc);
425    }
426}
427
428
429BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
430    : cpu(_cpu), interval(_interval)
431{ }
432
433void
434BaseCPU::ProfileEvent::process()
435{
436    ThreadID size = cpu->threadContexts.size();
437    for (ThreadID i = 0; i < size; ++i) {
438        ThreadContext *tc = cpu->threadContexts[i];
439        tc->profileSample();
440    }
441
442    cpu->schedule(this, curTick() + interval);
443}
444
445void
446BaseCPU::serialize(std::ostream &os)
447{
448    SERIALIZE_SCALAR(instCnt);
449    interrupts->serialize(os);
450}
451
452void
453BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
454{
455    UNSERIALIZE_SCALAR(instCnt);
456    interrupts->unserialize(cp, section);
457}
458
459void
460BaseCPU::traceFunctionsInternal(Addr pc)
461{
462    if (!debugSymbolTable)
463        return;
464
465    // if pc enters different function, print new function symbol and
466    // update saved range.  Otherwise do nothing.
467    if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
468        string sym_str;
469        bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
470                                                         currentFunctionStart,
471                                                         currentFunctionEnd);
472
473        if (!found) {
474            // no symbol found: use addr as label
475            sym_str = csprintf("0x%x", pc);
476            currentFunctionStart = pc;
477            currentFunctionEnd = pc + 1;
478        }
479
480        ccprintf(*functionTraceStream, " (%d)\n%d: %s",
481                 curTick() - functionEntryTick, curTick(), sym_str);
482        functionEntryTick = curTick();
483    }
484}
485
486bool
487BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
488{
489    panic("BaseCPU doesn't expect recvTiming callback!");
490    return true;
491}
492
493void
494BaseCPU::CpuPort::recvRetry()
495{
496    panic("BaseCPU doesn't expect recvRetry callback!");
497}
498
499Tick
500BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
501{
502    panic("BaseCPU doesn't expect recvAtomic callback!");
503    return curTick();
504}
505
506void
507BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
508{
509    // No internal storage to update (in the general case). In the
510    // long term this should never be called, but that assumed a split
511    // into master/slave and request/response.
512}
513
514void
515BaseCPU::CpuPort::recvRangeChange()
516{
517}
518